Semiconductor integrated circuit and layout designing method of the same
View Patent ↗A semiconductor integrated circuit of the present invention comprises a hard macro and a plurality of wirings connected to the hard macro. The hard macro comprises a hard macro main body, and a plurality of pins with a minimum pin width based on a design rule of the semiconductor integrated circuit, which is connected to the wirings. Each of the pins is arranged in a vicinity of the peripheral edge of the hard macro main body with a minimum isolated space based on the design rule provided therebetween along a direction crossing with a width direction of the peripheral edge. The wirings are arranged obliquely along a direction crossing with a perpendicular direction of the peripheral edge.
1. A semiconductor integrated circuit, comprising a hard macro, a plurality of logic cells and a plurality of wirings, wherein:
said hard macro includes a hard macro main body, and a plurality of pins connected to said hard macro main body;
each of said plurality of wirings is connected to one of said plurality of pins and to one of said plurality of logic cells;
said plurality of pins include at least three first-type pins and at least three second-type pins;
said first-type pins, each of which is adjacent to one of said first-type pins, are arranged along a first direction;
said second-type pins, each of which is adjacent to one of said second-type pins, are arranged along a second direction;
said first direction is oblique to said second direction on a plane;
wherein:
said plurality of wirings include first-type wirings and second-type wirings;
each of said first-type wirings is arranged along a third direction;
each of said second-type wirings is arranged along a fourth direction;
said third direction is oblique to said fourth direction on the plane;
each of said first-type wirings is connected to one of said first-type pins; and
each of said second-type wirings is connected to one of said second-type pins.
2. The semiconductor integrated circuit of claim 1 , wherein:
said third direction is at an angle of 45 degrees relative to said fourth direction.
3. The semiconductor integrated circuit of claim 1 , wherein:
said first direction is oblique to peripheral edges of said hard macro main body.
4. The semiconductor integrated circuit of claim 3 , wherein:
said second direction is oblique to said peripheral edges of said hard macro main body.
5. The semiconductor integrated circuit of claim 1 , wherein:
said first-type pins are provided in a vicinity of a first peripheral edge of said hard macro main body;
said second-type pins are provided in a vicinity of a second peripheral edge of said hard macro main body; and
said first peripheral edge is opposed to said second peripheral edge.
6. The semiconductor integrated circuit of claim 1 , wherein:
a first peripheral edge of said hard macro main body is opposed to a second peripheral edge of said hard macro main body;
said first-type pins include pins provided in a vicinity of one-end side of said first peripheral edge and other pins provided in a vicinity of an other-end side of said second peripheral edge; and
said second-type pins include pins provided in a vicinity of an other-end side of said first peripheral edge and other pins provided in a vicinity of one-end side of said second peripheral edge.
7. The semiconductor integrated circuit of claim 6 , wherein:
said first direction is along said first peripheral edge.