IP Library Granted Patent US 7,739,552
Granted Patent B2
US 7,739,552 · App. 11/552,125 · Granted Jun 15, 2010

Tapping a memory card

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Quick Facts
Patent No.
US 7,739,552
App. No.
11/552,125
Granted
Jun 15, 2010
Kind
B2
Abstract

A protocol analyzer for analyzing traffic on a bus. A system includes a tap, a pod and an analyzer. The tap includes differential inputs for the bus. One of the differential inputs is a line from the bus and the other is a reference input that has been divided. The reference input enables the system to determine whether data on the bus is high or low even in situations where the operating voltage of the bus is unknown.

Claims (26)

1. An apparatus for tapping a system that includes a host and a card, the apparatus comprising:

a first end that connects with a host;

a second end that connects with a card;

a pass through bus connecting the first end and the second end such that the host continues to operate with the card over the pass through bus;

a repeater that connects to the pass through bus, the repeater having a differential input, a first input of the differential input connected with a line of the bus and a second input of the differential input connected to a reference voltage that enables a signal on the line of the bus to be identified as a high signal or a low signal without knowing a value of the high signal;

an interface voltage circuit that generates the reference voltage provided to the second input of the differential input;

a pod that removably connects with the apparatus and that removably connects with a protocol analyzer;

a tap that removably connects to the pod and one of the following:

a memory that stores an ID, the ID corresponding to a protocol for which the apparatus is configured; or

a hard-coded ID.

2. The apparatus of claim 1 , wherein the interface voltage circuit receives an input from the bus that corresponds to a high signal.

3. The apparatus of claim 2 , wherein the input from the bus received by the interface voltage circuit comprises a Vcc of the bus.

4. The apparatus of claim 1 , wherein the pod receives the ID from the memory or from the hard-coded ID and generates a signal that includes the received ID such that the protocol analyzer can interpret data tapped from the bus and wherein the pod comprises an FPGA that can be prepared for multiple protocols such that more than one type of tap can be used with the pod.

5. The apparatus of claim 1 , further comprising a second repeater, each repeater having a plurality of differential inputs.

6. The apparatus of claim 5 , wherein a first input in each of the plurality of differential inputs receives a reference voltage from an interface voltage circuit.

7. The apparatus of claim 6 , wherein a comparison of a signal on the bus with the reference voltage determines if the signal on the bus is high or low.

8. The apparatus of claim 6 , wherein the repeater has an output for each differential input, each output being a single ended output or a low voltage differential output.

9. The apparatus of claim 6 , wherein the interface voltage circuit is a voltage divider that divides a Vcc of the bus to about 0.625 volts.

10. The apparatus of claim 1 , wherein the card is a SD (Secure Digital Card), SDIO (SD Input/Output Card), MMC (Multimedia Card), or CE-ATA (Consumer Electronics-Advanced Technology Attachment) card.

11. The apparatus of claim 1 , wherein the pass through bus comprises data lines, command lines, a clock, voltages provided by a host to a device or any combination thereof.

12. The apparatus of claim 1 , wherein the host is a personal digital assistant, a digital camera, a personal audio player, a digital media player, a digital recorder, a cellular telephone, or a laptop computer or any combination thereof.

13. The apparatus of claim 1 , wherein the pod includes an FPGA that processes signals from the bus of the system being analyzed.

14. The apparatus of claim 1 , wherein the pod is integrated with the protocol analyzer.

15. The apparatus of claim 1 , wherein the pod includes control status indicators.

16. The apparatus of claim 6 , wherein the tap is configured such that the bus lines are tapped to branch the bus lines and corresponding signals off to the repeater.

17. The apparatus of claim 1 , wherein the tap is a non-intrusive pass-through tap.

Assignments (8)
RELEASE OF SECURITY INTEREST AT REEL/FRAME 73189/0873 Recorded May 28, 2026
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: INERTIAL LABS, INC.; VIAVI SOLUTIONS INC.; VIAVI SOLUTIONS LICENSING LLC
Reel/Frame 075642/0381 →
SECURITY INTEREST Recorded Nov 14, 2025
From: VIAVI SOLUTIONS INC.; VIAVI SOLUTIONS LICENSING LLC; INERTIAL LABS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS AGENT
Reel/Frame 073571/0137 →
SECURITY AGREEMENT Recorded Oct 21, 2025
From: INERTIAL LABS, INC.; VIAVI SOLUTIONS INC.; VIAVI SOLUTIONS LICENSING LLC
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 073189/0873 →
TERMINATIONS OF SECURITY INTEREST AT REEL 052729, FRAME 0321 Recorded Jan 5, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: VIAVI SOLUTIONS INC.; RPC PHOTONICS, INC.
Reel/Frame 058666/0639 →
SECURITY INTEREST Recorded May 21, 2020
From: VIAVI SOLUTIONS INC.; 3Z TELECOM, INC.; ACTERNA LLC; ACTERNA WG INTERNATIONAL HOLDINGS LLC; VIAVI SOLUTIONS LLC; JDSU ACTERNA HOLDINGS LLC; OPTICAL COATING LABORATORY, LLC; RPC PHOTONICS, INC.; TTC INTERNATIONAL HOLDINGS, LLC
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 052729/0321 →
CHANGE OF NAME Recorded Nov 6, 2015
From: JDS UNIPHASE CORPORATION
To: VIAVI SOLUTIONS INC.
Reel/Frame 037057/0627 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2012
From: FINISAR CORPORATION
To: JDS UNIPHASE CORPORATION
Reel/Frame 028269/0334 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2007
From: LANNING, ERIC
To: FINISAR CORPORATION
Reel/Frame 018928/0865 →