Data processing device adaptable to variable external memory size and endianess

1. A data processing device comprising an external memory for storing data defining at least part of a program in an Endian form, and an integrated circuit coupled to said external memory via a memory bus having an N-bit width, and comprising i) an embedded processor adapted to run with said program, ii) an internal memory for storing at least a bootstrap code of said program, iii) an external memory interface coupled to said memory bus and iv) a processor bus coupling said internal memory and said external memory interface to said embedded processor, wherein said external memory is arranged to store, at a chosen address, an N-bit data word having a value representative of its size, equal to N/8 bits, and of the Endian form of the stored program data, and in that it also comprises a configuration means coupled to said embedded processor and to said external memory interface and arranged to deduce from at least one part of 8 bits of said N-bit data word, read by said external memory interface at the chosen address of said external memory, the size and the Endian form of storage of said external memory and to set the width of said external memory interface according to said deduced external memory size and a data processing mode of said embedded processor according to said deduced Endian form of storage, and wherein said configuration means is arranged to generate N/8 8-bit accesses to said external memory at consecutive addresses starting from said chosen address to read at least said one part of said N-bit data word, and in that said embedded processor comprises a dedicated memory having a size equal to N and arranged to store each read part of said N-bit data word at N/8 consecutive addresses.

2. The data processing device according to claim 1 , wherein said configuration means is arranged to control said external memory interface to preset it to an 8-bit width in order for the interface to access said external memory at said chosen address to read said part(s) of 8 bits of said stored N-bit data word.

3. The data processing device according to claim 1 , wherein said configuration means is arranged to preset in Little-Endian form the data processing mode of said embedded processor before reading of said N-bit data word in said external memory.

4. The data processing device according to claim 3 , wherein said configuration means is arranged either to confirm said presetting of the data processing mode of said embedded processor in Little-Endian form when said deduced Endian form of storage is Little-Endian, or to set the data processing mode of said embedded processor in Big-Endian form when said deduced Endian form of storage is Big-Endian.

5. The data processing device according to claim 1 , wherein said configuration means is arranged to preset in Big-Endian form the data processing mode of said embedded processor before reading of said N-bit data word in said external memory.

6. The data processing device according to claim 5 , wherein said configuration means is arranged either to confirm said presetting of the data processing mode of said embedded processor in Big-Endian form when said deduced Endian form of storage is Big-Endian, or to set the data processing mode of said embedded processor in Little-Endian form when said deduced Endian form of storage is Little-Endian.

7. The data processing device according to claim 1 , wherein, when N is equal to 32 and said external memory size is equal to 32, said configuration means is arranged to generate four 8-bit accesses to said external memory at four consecutive addresses starting from said chosen address to read a first part of said N-bit data word four times, and in that said dedicated memory is arranged to store said read first part of said N-bit data word in first, second, third and fourth consecutive addresses, whatever the deduced Endian form.

8. The data processing device according to claim 1 , wherein, when N is equal to 32 and said external memory size is equal to 16, said configuration means is arranged to generate four 8-bit accesses to said external memory at four consecutive addresses starting from said chosen address to read a first part and a third part of said N-bit data word two times, and in that said dedicated memory is arranged to store either the read first part at consecutive first and second addresses of the dedicated memory and the read third part at third and fourth consecutive addresses when said deduced Endian form of storage is Little-Endian, or the read third part at first and second consecutive addresses and the read first part at third and fourth consecutive addresses when said deduced Endian form of storage is Big-Endian.

9. The data processing device according to claim 1 , wherein, when N is equal to 32 and said external memory size is equal to 8, said configuration means is arranged to generate four 8-bit accesses to said external memory at four consecutive addresses starting from said chosen address to read first, second, third and fourth consecutive parts of said N-bit data word, and in that said dedicated memory is arranged to store either said first, second, third and fourth parts respectively at first, second, third and fourth consecutive addresses when said deduced Endian form of storage is Little-Endian, or said first, second, third and fourth parts respectively at said fourth, third, second and first addresses, when said deduced Endian form of storage is Big-Endian.

10. A mobile phone, comprising in a data processing device comprising an external memory for storing data defining at least part of a program in an Endian form, and an integrated circuit coupled to said external memory via a memory bus having an N-bit width, and comprising i) an embedded processor adapted to run with said program, ii) an internal memory for storing at least a bootstrap code of said program, iii) an external memory interface coupled to said memory bus and iv) a processor bus coupling said internal memory and said external memory interface to said embedded processor, wherein said external memory is arranged to store, at a chosen address, an N-bit data word having a value representative of its size, equal to N/8 bits, and of the Endian form of the stored program data, and in that it also comprises a configuration module coupled to said embedded processor and to said external memory interface and arranged to deduce from at least one part of 8 bits of said N-bit data word, read by said external memory interface at the chosen address of said external memory, the size and the Endian form of storage of said external memory and to set the width of said external memory interface according to said deduced external memory size and a data processing mode of said embedded processor according to said deduced Endian form of storage, and wherein said configuration module is arranged to generate N/8 8-bit accesses to said external memory at consecutive addresses starting from said chosen address to read at least said one part of said N-bit data word, and in that said embedded processor comprises a dedicated memory having a size equal to N and arranged to store each read part of said N-bit data word at N/8 consecutive addresses.

11. The mobile phone according to claim 10 , wherein said configuration module is arranged to control said external memory interface to preset it to an 8-bit width in order for the interface to access said external memory at said chosen address to read said part(s) of 8 bits of said stored N-bit data word.

12. The mobile phone according to claim 10 , wherein said configuration module is arranged to preset in Little-Endian form the data processing mode of said embedded processor before reading of said N-bit data word in said external memory.

13. The mobile phone according to claim 12 , wherein said configuration module is arranged either to confirm said presetting of the data processing mode of said embedded processor in Little-Endian form when said deduced Endian form of storage is Little-Endian, or to set the data processing mode of said embedded processor in Big-Endian form when said deduced Endian form of storage is Big-Endian.

14. The mobile phone according to claim 10 , wherein said configuration module is arranged to preset in Big-Endian form the data processing mode of said embedded processor before reading of said N-bit data word in said external memory.

15. The mobile phone according to claim 14 , wherein said configuration module is arranged either to confirm said presetting of the data processing mode of said embedded processor in Big-Endian form when said deduced Endian form of storage is Big-Endian, or to set the data processing mode of said embedded processor in Little-Endian form when said deduced Endian form of storage is Little-Endian.

16. The mobile phone according to claim 10 , wherein, when N is equal to 32 and said external memory size is equal to 32, said configuration module is arranged to generate four 8-bit accesses to said external memory at four consecutive addresses starting from said chosen address to read a first part of said N-bit data word four times, and in that said dedicated memory is arranged to store said read first part of said N-bit data word in first, second, third and fourth consecutive addresses, whatever the deduced Endian form.

17. The mobile phone according to claim 10 , wherein, when N is equal to 32 and said external memory size is equal to 16, said configuration module is arranged to generate four 8-bit accesses to said external memory at four consecutive addresses starting from said chosen address to read a first part and a third part of said N-bit data word two times, and in that said dedicated memory is arranged to store either the read first part at consecutive first and second addresses of the dedicated memory and the read third part at third and fourth consecutive addresses when said deduced Endian form of storage is Little-Endian, or the read third part at first and second consecutive addresses and the read first part at third and fourth consecutive addresses when said deduced Endian form of storage is Big-Endian.

18. The mobile phone according to claim 10 , wherein, when N is equal to 32 and said external memory size is equal to 8, said configuration module is arranged to generate four 8-bit accesses to said external memory at four consecutive addresses starting from said chosen address to read first, second, third and fourth consecutive parts of said N-bit data word, and in that said dedicated memory is arranged to store either said first, second, third and fourth parts respectively at first, second, third and fourth consecutive addresses when said deduced Endian form of storage is Little-Endian, or said first, second, third and fourth parts respectively at said fourth, third, second and first addresses, when said deduced Endian form of storage is Big-Endian.

19. A data processing device comprising an external memory for storing data defining at least part of a program in an Endian form, and an integrated circuit coupled to said external memory via a memory bus having an N-bit width, and comprising i) an embedded processor adapted to run with said program, ii) an internal memory for storing at least a bootstrap code of said program, iii) an external memory interface coupled to said memory bus and iv) a processor bus coupling said internal memory and said external memory interface to said embedded processor, wherein said external memory is arranged to store, at a chosen address, an N-bit data word having a value representative of its size, equal to N/M bits, and of the Endian form of the stored program data, and in that it also comprises a configuration means coupled to said embedded processor and to said external memory interface and arranged to deduce from at least one part of M bits of said N-bit data word, read by said external memory interface at the chosen address of said external memory, the size and the Endian form of storage of said external memory and to set the width of said external memory interface according to said deduced external memory size and a data processing mode of said embedded processor according to said deduced Endian form of storage, and wherein said configuration means is arranged to generate N/M M-bit accesses to said external memory at consecutive addresses starting from said chosen address to read at least said one part of said N-bit data word.