Data processing system and method for memory arbitration
The present invention relates to a data processing system is provided which comprises at least one first processing unit (CPU), at least one second processing unit (PU), at least one memory module (MEM), and an interconnect. The memory module (MEM) serves to store data from said at least one first and second processing unit (CPU, PU). The interconnecting means couples the memory module (MEM) to the first and second processing units (CPU, PU). In addition, an arbitration unit (AU) is provided for performing the arbitration to the memory module (MEM) of the first and second processing units (CPU, PU). The arbitration is performed on a time window basis. A first access time during which the second processing unit (PU) has accessed the memory module and a second access time which is still required by the second processing unit (PU) to complete its processing are monitored during a predefined time window by the arbitration unit (AU). The second access time is compared to the remaining access time in the time window and if the remaining access time is larger than the second access time, the arbitration unit (AU) allows said at least one first processing unit (CPU) to access the memory module in said time window. Otherwise, the arbitration unit (AU) restricts the access of the at least one first processing units (CPU) and allows the at least one second processing unit (PU) to access the memory module (MEM).
1. A data processing system comprising:
at least one first processing unit configured to perform latency critical processing;
at least one second processing unit configured to perform real time processing;
at least one memory module for storing data from said at least one first and second processing unit;
an interconnect means for coupling said memory module to the first and second processing units; and
an arbitration unit for arbitrating for access to the memory module for the first and second processing units on a time window basis by monitoring a first access time during which the second processing unit has accessed the memory module and a second access time which is required by the second processing unit to complete its processing during a predefined time window, and by comparing the second access time to the remaining access time in the time window,
wherein said arbitration unit is configured to allow said at least one first processing unit to access the memory module in said time window if the remaining access time is larger than the second access time, and allows the at least one second processing unit to access the memory module if the remaining access time is not larger than the second access time,
wherein said arbitration unit is configured to first give a high priority to latency critical traffic from said at least one first processing unit in order to provide a low latency access, and to place traffic of the at least one second processing unit in any empty time slots during which the latency critical traffic is not present, and
wherein during the process of a time window the arbitration unit is configured to switch a priority to the traffic of the at least one second processing unit if the latency critical traffic requests access to the at least one memory module such that the arbitration unit detects that a programmed real-time requirement is close to being violated, so as to provide a bandwidth guarantee for the traffic of the at least one second processing unity and to only provide a latency hit when an actual threat of violating the real-time requirements is present.
2. A data processing system according to claim 1 , wherein
the second access time can be determined during run time based on traffic characteristics of the at least second processing unit.
3. A memory controller for controlling the access to an external memory, wherein the memory controller receives access requests for said external memory from at least one first and at least one second processing unit, the at least one first processing unit being configured to perform latency critical processing, and the at least one second processing unit being configured to perform real time processing, comprising:
an arbitration unit for arbitrating access to the memory module for the first and second processing units on a time window basis by monitoring a first access time during which the second processing unit has accessed the memory module and a second access time which is required by the second processing unit to complete its processing during a predefined time window, and by comparing the second access time to the remaining access time in the time window,
wherein said arbitration unit is configured to allow said at least one first processing unit to access the memory module in said time window, if the remaining access time is larger than the second access time, and allows the at least one second processing unit to access the memory module if the remaining access time is not larger than the second access time,
wherein said arbitration unit is configured to first give a high priority to latency critical traffic from said at least one first processing unit in order to provide a low latency access, and to place traffic of the at least one second processing unit in any empty time slots during which the latency critical traffic is not present, and
wherein during the process of a time window the arbitration unit is configured to switch a priority to the traffic of the at least one second processing unit if the latency critical traffic requests access to the at least one memory module such that the arbitration unit detects that a programmed real-time requirement is close to being violated, so as to provide a bandwidth guarantee for the traffic of the at least one second processing unity and to only provide a latency hit when an actual threat of violating the real-time requirements is present.
4. A method for arbitrating for access to a memory module for at least one first and at least one second processing unit on a time window basis, the at least one first processing unit being configured to perform latency critical processing, and the at least one second processing unit being configured to perform real time processing, comprising the steps of:
monitoring a first access time during which the second processing unit has accessed the memory module,
monitoring a second access time which is required by the second processing unit to complete its processing during a predefined time window, and
comparing the second access time to the remaining access time in the time window during a predefined time window,
wherein said at least one first processing unit is allowed to access the memory module in said time window if the remaining access time is larger than the second access time, and the at least one second processing unit is allowed to access the memory module if the remaining access time is not larger than the second access time,
wherein said arbitration unit is configured to first give a high priority to latency critical traffic from said at least one first processing unit in order to provide a low latency access, and to place traffic of the at least one second processing unit in any empty time slots during which the latency critical traffic is not present, and
wherein during the process of a time window the arbitration unit is configured to switch a priority to the traffic of the at least one second processing unit if the latency critical traffic requests access to the at least one memory module such that the arbitration unit detects that a programmed real-time requirement is close to being violated, so as to provide a bandwidth guarantee for the traffic of the at least one second processing unity and to only provide a latency hit when an actual threat of violating the real-time requirements is present.