IP Library Granted Patent US 8,901,703
Granted Patent B2
US 8,901,703 · App. 11/579,679 · Granted Dec 2, 2014

Electronic device

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Quick Facts
Patent No.
US 8,901,703
App. No.
11/579,679
Granted
Dec 2, 2014
Kind
B2
Abstract

The electronic device comprises a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material. The substrate has a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface layer on its first side. A first and a second lateral pin diode are defined in the substrate, each of the pin diodes having a doped p-region, a doped n-region and an intermediate intrinsic region. The intrinsic region of the first pin diode is larger than that of the second pin diode.

Claims (17)

1. An electronic device comprising a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material, the substrate having a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface layer on its first side; wherein a first and a second lateral pin diode are defined in the substrate, each of the pin diodes having a doped p-region, a doped n-region and an intermediate intrinsic region arranged laterally between the doped p-region and the doped n-region of each pin diode, and of which pin diodes the intrinsic region of the first pin diode having a larger width than that of the second pin diode, and a resistance of the first pin diode is larger than a resistance of the second pin diode; and wherein a crystal lattice of the substrate includes crosstalk-mitigating lattice defects created by irradiation of the substrate, the crosstalk-mitigating lattice defects being an amorphisation of the substrate and being configured to act as a recombination region for ions originating from one of the pin diodes to prevent crosstalk between the first pin diode and the second pin diode; and

wherein an external input is connected to an anode of the second pin diode and the first and second pin diodes are connected in series in a same anode-cathode orientation without a further pin diode connected between the first and second pin diodes.

2. An electronic device as claimed in claim 1 , wherein the substrate is provided with means for preventing crosstalk between the first and the second pin diode.

3. An electronic device as claimed in claim 2 , wherein the means for preventing crosstalk comprise an isolation of a substrate portion in which the first pin diode is defined, which isolation comprises a buried layer in the substrate.

4. An electronic device as claimed in claim 2 , wherein the crosstalk-mitigating lattice defects in the substrate are created by irradiating the substrate by beams of electromagnetic radiation in particles.

5. An electronic device as claimed in claim 2 , wherein the means for preventing cross talk comprise electrically conductive particles.

6. An electronic device as claimed in claim 1 , wherein the first pin diode has a substantially circular or oval shape in a cross section parallel to the substrate surface.

7. An electronic device as claimed in claim 6 , wherein the doped n-region is laterally present inside the intrinsic region.

8. An electronic device as claimed in claim 6 , wherein the circular or oval shape is provided with a gap, and wherein an interconnect for connecting a region of the first pin diode is located such that on perpendicular projection of the interconnect on the substrate surface there is a substantial overlap with the gap.

9. An electronic device as claimed in claim 1 , wherein the at least one inductor and the capacitor are embedded in a stack comprising a first and a second electrically conductive layer and a dielectric layer and an insulating layer there between, said insulating layer acting as a spacer and comprising contact windows for connecting an electrode of the capacitor.

10. An electronic device as claimed in claim 1 , wherein the first pin diode is arranged in a receive path of an antenna switch, and the second pin diode is arranged in a transmit path of an antenna circuit.

11. An electronic device as claimed in claim 1 , wherein the substrate is silicon and the substrate has a resistivity greater than or equal to 4 kΩ.cm.

12. The electronic device of claim 1 , wherein the lattice defects are located within an Si bandgap of the substrate, and configured and arranged with localized energy states.

13. The electronic device of claim 1 , wherein the lattice defects are configured and arranged with ion implants at the substrate surface.

14. The electronic device of claim 1 , wherein the lattice defects are configured and arranged with embedded conductive particles in the substrate.

15. The electronic device of claim 1 , wherein a portion of the substrate containing the lattice defects has an effective resistance that is greater than the substrate by a factor of 10,000 compared to untreated high-ohmic silicon.

16. The electronic device of claim 1 , wherein the lattice defects of the crystal lattice are defined by permanent radiation damage.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2015
From: NXP B.V.
To: III HOLDINGS 6, LLC
Reel/Frame 036304/0330 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2006
From: DEN DEKKER, ARNOLDUS; DIJKHUIS, JOHANNES, F.; PULSFORD, NICOLAS J.; VAN BEEK JOZEF, T., M.; ROOZEBOOM, FREDDY; KEMMEREN, ANTONIUS L., A., M.; KLOOTWIJK, JOHAN H.; NOLLEN, MAARTEN, D-J.
To: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
Reel/Frame 018600/0635 →