Semiconductor memory comprising dual charge storage nodes and methods for its fabrication

1. A method for fabricating a semiconductor memory comprising dual charge storage nodes overlying a semiconductor substrate, the method comprising the steps of:

forming a dielectric plug comprising a first portion recessed into the semiconductor substrate and a second portion extending above the semiconductor substrate;

growing a layer of semiconductor material overlying the second portion;

forming a first layered structure overlying a first side of the second portion of the dielectric plug and a second layered structure overlying a second side of the second portion of the dielectric plug, each of the first layered structure and the second layered structure overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers, implanting conductivity determining ions into the substrate to form a first bit line adjacent the first side and a second bit line adjacent the second side;

depositing and patterning a layer of conductive material to form a control gate overlying the dielectric plug, the first layered structure, and the second layered structure; and

forming a layer of gate insulator material overlying the layer of semiconductor material.

2. The method of claim 1 wherein the step of forming a first layered structure overlying a first side of the second portion of the dielectric plug and a second layered structure overlying a second side of the second portion of the dielectric plug comprises the steps of:

forming a layer of tunnel oxide overlying the layer of semiconductor material;

depositing a layer of charge storage material overlying the layer of tunnel oxide;

anisotropically etching the layer of charge storage material; and

forming a second dielectric layer overlying the anisotropically etched layer of charge storage material.

3. The method of claim 2 wherein the step of depositing a layer of charge storage material comprises the step of depositing a layer of silicon rich nitride.

4. The method of claim 1 wherein the step of forming a dielectric plug comprises the steps of:

forming a patterned layer of hard mask material overlying the semiconductor substrate;

etching the semiconductor substrate using the patterned layer of hard mask material as an etch mask to form a trench extending into the semiconductor substrate;

filling the trench with a dielectric fill material; and

removing the patterned layer of hard mask material.

5. The method of claim 1 wherein the step of growing a layer of semiconductor material comprises the step of growing a layer of monocrystalline semiconductor material.

6. A method for fabricating a semiconductor memory comprising dual charge storage nodes overlying a semiconductor substrate, the method comprising the steps of:

embedding a dielectric plug into the semiconductor substrate, the dielectric plug having a top portion, a first side and a second side;

forming a layer of semiconductor material overlying the semiconductor substrate and the top portion, the first side and the second side of the dielectric plug;

forming a layered structure comprising a first dielectric layer, a deposited charge storage layer overlying the first dielectric layer, and a second dielectric layer overlying the charge storage layer, one portion of the layered structure formed overlying the layer of semiconductor material adjacent a first side of the dielectric plug and a second portion of the layered structure formed overlying the layer of semiconductor material adjacent a second side of the dielectric plug;

forming a gate insulator overlying a portion of the layer of semiconductor material adjacent the top portion of the dielectric plug;

forming a first bit line in the semiconductor substrate aligned with the first portion;

forming a second bit line in the semiconductor substrate aligned with the second portion; and

depositing and patterning a layer of conductive material to form a control gate overlying the first portion, the second portion, and the gate insulator.

7. The method of claim 6 wherein the step of forming a layer of semiconductor material comprises the step of epitaxially growing a monocrystalline layer comprising silicon.

8. The method of claim 6 wherein the step of forming a layer of semiconductor material comprises the steps of:

depositing a layer of semiconductor material comprising a semiconductor material selected from the group consisting of amorphous silicon and polycrystalline silicon; and

heat treating the layer of semiconductor material to crystallize the layer of material to monocrystalline silicon.

9. The method of claim 6 wherein the step of embedding a dielectric plug comprise the steps of:

depositing and patterning a layer of hard mask material overlying the semiconductor substrate;

etching a trench extending into the semiconductor substrate using the layer of hard mask material as an etch mask;

depositing a layer of dielectric fill material to fill the trench;

planarizing the layer of dielectric fill material by chemical mechanical planarization (CMP) using the layer of hard mask material as a CMP stop; and

removing the layer of hard mask material.

10. The method of claim 6 wherein the step of forming a layered structure comprises the steps of:

growing a layer of tunnel oxide at a surface of the semiconductor substrate;

depositing a layer comprising silicon nitride overlying the layer of tunnel oxide;

anisotropically etching the layer comprising silicon nitride; and

depositing a layer of silicon oxide overlying the layer comprising silicon nitride.

11. The method of claim 6 wherein the step of forming a gate insulator comprises the step of thermally oxidizing the layer of semiconductor material.

12. A method for fabricating a semiconductor memory comprising dual charge storage nodes and a semiconductor substrate having a surface, the method comprising the steps of:

forming a dielectric plug having a recessed portion extending below the surface and a raised portion extending above the surface, the raised portion having a first side, a second side, and a top;

growing a layer of semiconductor material overlying the surface and the raised portion;

forming a tunnel dielectric layer on the layer of semiconductor material;

depositing a layer of charge storage material overlying the tunnel dielectric layer;

anisotropically etching the layer of charge storage material to form a first region of charge storage material adjacent a first edge and a second region of charge storage material adjacent a second edge;

implanting conductivity determining ions into the substrate to form a first bit line on one side of the dielectric plug and a second bit line on an opposite side of the dielectric plug;

depositing a second layer of dielectric material overlying the first region and the second region;

depositing a layer of conductive material overlying the layer of dielectric material;

patterning the layer of conductive material to form a control gate overlying the first region of charge storage material, the second region of charge storage material, and the raised portion; and

forming a gate insulator layer overlying the layer of semiconductor material overlying the raised portion.

13. The method of claim 12 wherein the semiconductor substrate comprises silicon and the step of growing a layer of semiconductor material comprises the step of epitaxially growing a layer of silicon.

14. The method of claim 12 wherein the semiconductor substrate comprises silicon and the step of growing a layer of semiconductor material comprises the steps of:

depositing a layer comprising a material selected from the group consisting of polycrystalline silicon and amorphous silicon; and

heat treating the layer comprising a semiconductor material to crystallize the semiconductor material to monocrystalline silicon.

15. The method of claim 12 wherein the step of depositing a layer of charge storage material comprises the step of depositing a layer of material selected from the group consisting of polycrystalline silicon, silicon nitride, and silicon rich nitride.

16. The method of claim 12 wherein the step of implanting conductivity determining ions comprises the step of implanting conductivity determining ions to form a first bit line and a second bit line separated by the recessed portion.

17. The method of claim 16 wherein the step of implanting conductivity determining ions comprises the step of implanting conductivity determining ions to form a first bit line and a second bit line each having a depth into the substrate less than the recessed portion.