Low area architecture in BCH decoder
View Patent ↗An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t−1)/(codeword_len−3)≦X<(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.
1. In a key equation solver block for a processor-based BCH decoder, the improvement comprising the key equation solver block having a number of multiplier units specified by X, where:
t *(7* t− 1)/(codeword_len−3)≦ X <(t+1),
where t is a non-zero number of transmission errors for the key equation solver block to correct using the processor, and codeword_len is a length, greater than 3, of a transmitted codeword to be decoded by the processor-based BCH decoder.