Method of forming spaced-apart charge trapping stacks

1. A method for fabricating a semiconductor memory device, the method comprising the steps of:

fabricating a plurality of spaced-apart charge-trapping stacks overlying a silicon substrate;

forming a plurality of bit line regions in the silicon substrate between the spaced-apart charge-trapping stacks;

fabricating a plurality of insulating elements overlying the exposed bit line regions and between the spaced-apart charge-trapping stacks;

etching a portion of each of the plurality of spaced-apart charge trapping stacks to form two complementary charge storage nodes from each of the charge trapping stacks and to expose a portion of the silicon substrate between the two complementary charge storage nodes;

growing silicon on the exposed portions of the silicon substrate by a process of selective epitaxial growth;

oxidizing at least a portion of the epitaxially grown silicon, and at least a portion of the silicon substrate underlying the epitaxially grown silicon; and

fabricating a control gate layer overlying the complementary charge storage nodes and the oxidized epitaxially grown silicon.

2. The method of claim 1 , wherein the step of fabricating a plurality of spaced apart charge-trapping stacks overlying the substrate comprises the steps of:

forming a first insulating layer overlying the substrate;

fabricating a charge trapping layer overlying the first insulating layer;

forming a second insulating layer overlying the charge trapping layer;

forming a patterned etch mask overlying the second insulating layer; and

anisotropically etching the second insulating layer, the charge trapping layer, and the first insulating layer.

3. The method of claim 2 , wherein the step of fabricating a charge trapping layer comprises the step of fabricating a layer of silicon nitride, silicon-rich silicon nitride, polycrystalline silicon, or a combination thereof.

4. The method of claim 1 , wherein the step of etching a portion of each of the plurality of spaced-apart charge trapping stacks comprises the steps of:

depositing a layer of material that has an etch property different from that of the second insulating layer overlying the charge-trapping stacks and the insulating elements;

anisotropically etching the layer of material to form sidewall spacers overlying a portion of the charge trapping stacks and adjacent sidewalls of the insulating elements; and

anisotropically etching the second insulating layer, the charge trapping layer, and the first insulating layer using the sidewall spacers as etch masks.

5. The method of claim 1 , wherein the step of fabricating a plurality of insulating elements comprises the steps of:

depositing a blanket layer of an insulating material overlying the spaced-apart charge trapping stacks and between the spaced-apart charge trapping stacks; and

planarizing the blanket layer to remove portions of the blanket layer overlying the charge trapping stacks.

6. The method of claim 1 , wherein the step of growing silicon comprises the steps of growing silicon to a thickness in the range of about 2 nm to about 15 nm.

7. The method of claim 1 , wherein the step of oxidizing a least a portion of the epitaxially grown silicon comprises the step of oxidizing substantially all of the epitaxially grown silicon.

8. The method of claim 1 , wherein the step of fabricating a plurality of insulating elements comprises the step of fabricating a plurality of insulating elements from high density plasma silicon oxide.

9. A method for fabricating a dual bit memory device, the method comprising the steps of:

forming a plurality of multi-layer charge-trapping stacks overlying a silicon substrate;

implanting impurity dopants into the silicon substrate to form a plurality of impurity-doped bit line regions between the multi-layer charge-trapping stacks;

fabricating a plurality of insulating elements, wherein each of the plurality of insulating elements overlies one of the plurality of bit line regions and is disposed between two adjacent charge-trapping stacks of the plurality of multi-layer charge-trapping stacks;

forming sidewall spacers overlying portions of the multi-layer charge-trapping stacks and adjacent sidewalls of each of the plurality of insulating elements;

etching portions of each of the plurality of multi-layer charge-trapping stacks using the sidewalls spacers as etching masks to expose portions of the silicon substrate;

growing silicon on the exposed portions of the silicon substrate by a process of selective epitaxial growth;

oxidizing the epitaxially grown silicon, and at least a portion of the silicon substrate underlying the epitaxially grown silicon; and

fabricating a control gate layer overlying the multi-layer charge trapping stacks and the oxidized silicon.

10. The method of claim 9 , wherein the step of implanting impurity dopants into a silicon substrate comprises the step of implanting arsenic ions or phosphorous ions into the silicon substrate.

11. The method of claim 9 , wherein the step of forming a plurality of multi-layer charge-trapping stacks comprises the steps of

forming a first insulating layer overlying the silicon substrate;

fabricating a charge trapping layer overlying the first insulating layer;

forming a second insulating layer overlying the charge trapping layer;

forming a patterned etch mask overlying the second insulating layer; and

anisotropically etching the second insulating layer, the charge trapping layer, and the first insulating layer.

12. The method of claim 11 , wherein the step of fabricating a charge trapping layer comprises the step of fabricating a layer of silicon nitride, silicon-rich silicon nitride, polycrystalline silicon, or a combination thereof.

13. The method of claim 9 , wherein the step of fabricating a plurality of insulating elements comprises the steps of:

depositing an insulating material layer overlying the charge-trapping stacks and the bit line regions; and

removing portions of the insulating material layer that overlie the charge-trapping stacks.

14. The method of claim 9 , wherein the step of forming sidewall spacers overlying portions of the plurality of multi-layer charge-trapping stacks and adjacent sidewalls of each of the plurality of insulating elements comprises the steps of:

depositing overlying the charge-trapping stacks and the insulating elements a conformal layer of a material that has an etch property that is different from that of a top surface of the charge-trapping stacks; and

anisotropically etching the conformal layer.

15. The method of claim 9 , wherein the step of growing silicon on the exposed portions of the silicon substrate comprises the step of growing silicon to a thickness in the range of about 2 nm to about 15 nm.

16. The method of claim 9 , wherein the step of oxidizing the epitaxially grown silicon comprises the step of partially oxidizing the epitaxially grown silicon.

17. The method of claim 9 , wherein the step of oxidizing the epitaxially grown silicon comprises the step of substantially fully oxidizing the epitaxially grown silicon.

18. A method for fabricating a semiconductor memory device, the method comprising the steps of:

providing a silicon substrate having spaced-apart bit line regions therein;

forming a first silicon oxide layer overlying the silicon substrate;

fabricating a silicon-rich silicon nitride layer overlying the first silicon oxide layer;

forming a second silicon oxide layer overlying the silicon-rich silicon nitride layer;

forming a patterned etch mask overlying the second silicon oxide layer;

anisotropically etching the second silicon oxide layer, the silicon-rich silicon nitride layer, and the first oxide layer to form multi-layer stacks overlying the silicon substrate;

fabricating bit line regions in the silicon substrate using the patterned etch mask as an ion implantation mask;

fabricating high density plasma silicon oxide (HDP) elements overlying the bit line regions and between the multi-layer stacks;

removing the patterned etch mask to expose portions of sidewalls of the HDP elements;

forming a conformal silicon nitride layer overlying the multi-layer stacks and the HDP elements;

anisotropically etching the conformal silicon nitride layer to form sidewall spacers overlying the multi-layer stacks and adjacent the exposed portions of the sidewalls of the HDP elements;

anisotropically etching the multi-layer stacks using the sidewall spacers as etch masks to form spaced-apart charge storage nodes and to expose portions of the silicon substrate;

growing silicon on the silicon substrate using selective epitaxial growth;

at least partially oxidizing the epitaxially grown silicon; and

depositing a polycrystalline silicon layer over the charge storage nodes, the oxidized silicon, and the HDP elements.

19. The method of claim 18 , wherein the step of at least partially oxidizing the epitaxially grown silicon comprises the step of oxidizing substantially all of the epitaxially grown silicon.

20. The method of claim 18 , wherein the step of at least partially oxidizing the epitaxially grown silicon comprises the step of oxidizing a portion of the silicon substrate underlying the epitaxially grown silicon.