Bus controller for handling split transactions
View Patent ↗A host controller is suitable for transferring data in transactions, each transaction being described by a transfer descriptor, and the transactions include split transactions. The transfer descriptor for a split transaction includes a bit which may be set to indicate whether the split transaction is a start split or a complete split transaction, and, once a transaction comprising split transactions has been started by a first split transaction, subsequent split transactions are generated automatically until the transaction is complete.
1. A device that executes split transactions, the device comprising:
a host microprocessor;
a system memory connected to the host microprocessor, wherein the host microprocessor transfers data to the system memory over a peripheral bus;
a Universal Serial Bus (USB) host controller connected to the host microprocessor and the system memory, wherein the USB host controller retrieves the data from the system memory and comprises:
an on-chip RAM connected to an interface, the on-chip RAM storing transfer descriptors sent from the host microprocessor,
registers that support the RAM, and
a host controller logic unit connected by an internal bus to the registers, wherein the USB host controller executes a single transfer descriptor from the on-chip RAM to transfer an entire USB payload across the interface and the transfer involves an amount of data specified by the single transfer descriptor without intervention by the host microprocessor;
wherein the single transfer descriptor handles both Start Split (SS) and Complete Split (CS) transactions.
2. The device of claim 1 , wherein, for a bulk transaction in which the data are transmitted via a hub for both SS and CS transactions, the device receives an acknowledgement message from the hub, and resets SS transactions into CS transactions in response to the acknowledgement message.
3. The device of claim 1 , wherein the device uses the single transfer descriptor to transfer up to 4K of the data to an endpoint device without intervention of the host microprocessor.
4. The device of claim 1 , wherein the on-chip RAM is a dual-port RAM.
5. The device of claim 4 , wherein the host microprocessor writes the data into a block while the USB host controller executes the transfer descriptor.
6. A method of transferring Universal Serial Bus (USB) data with a host controller, the method comprising:
using a host microprocessor to transfer data to a system memory over a peripheral bus;
using a USB host controller to retrieve the data from the system memory;
using an on-chip RAM in the USB host controller to store transfer descriptors sent from the host microprocessor;
using the USB host controller to execute a single transfer descriptor from the on-chip RAM to transfer an entire USB payload across an interface, wherein the transfer involves an amount of data specified by the single transfer descriptor without intervention by the host microprocessor; and
handling both Start Split (SS) and Complete Split (CS) transactions with the single transfer descriptor.
7. The method of claim 6 , for a bulk transaction in which the data are transmitted via a hub for both SS and CS transactions, further comprising:
receiving an acknowledgement message from the hub; and
resetting SS transactions into CS transactions in response to the acknowledgement message.
8. The method of claim 6 , further comprising:
using the single transfer descriptor to transfer up to 4K of the data to an endpoint device without intervention of the host microprocessor.
9. The method of claim 6 , wherein the on-chip RAM is a dual-port RAM.
10. The method of claim 9 , further comprising:
writing the data into a block with the host microprocessor while the host controller executes the transfer descriptor.
11. A Universal Serial Bus (USB) host controller that handles split transactions, wherein the USB host controller comprises:
an on-chip RAM connected to an interface, the on-chip RAM storing transfer descriptors sent from a host microprocessor;
registers that support the RAM; and
a host controller logic unit connected by an internal bus to the registers, wherein the USB host controller executes a single transfer descriptor from the on-chip RAM to transfer an entire USB payload across the interface, the transfer involving an amount of data specified by the single transfer descriptor without any intervention by the host microprocessor;
wherein the single transfer descriptor handles both Start Split (SS) and Complete Split (CS) transactions.
12. The host controller of claim 11 , wherein, for a bulk transaction in which the data are transmitted via a hub for both SS and CS transactions, the host controller receives an acknowledgement message from the hub, and resets SS transactions into CS transactions in response to the acknowledgement message.
13. The host controller of claim 11 , wherein the host controller uses the single transfer descriptor to transfer up to 4K of the data to an endpoint device without intervention of the host microprocessor.
14. The host controller of claim 11 , wherein the on-chip RAM is a dual-port RAM.
15. The host controller of claim 14 , wherein the host microprocessor writes the data into a block while the USB host controller executes the transfer descriptor.