IP Library Granted Patent US 7,930,481
Granted Patent B1
US 7,930,481 · App. 11/642,005 · Granted Apr 19, 2011

Controlling cached write operations to storage arrays

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Quick Facts
Patent No.
US 7,930,481
App. No.
11/642,005
Granted
Apr 19, 2011
Kind
B1
Abstract

An application may issue write operations intended for a SAN via a server cache. Monitoring of the SAN (e.g., the autonomous persistent cache of the storage arrays of the SAN), allows caching performance to be controlled by a write caching policy. The server cache memory may be increased, decreased or eliminated according to the write caching policy. In one embodiment, a storage volume manager may adjust the latency of write operations in the server cache. In some embodiments, the write caching policy may adapt and learn characteristics of the storage environment, which may include calibrated values for messaging timestamps.

Claims (38)

1. A method, comprising:

a computer system receiving a plurality of write operations directed to a storage area network (SAN) via a system cache implemented in a memory of the computer system, wherein the write operations are issued by an application running on the computer system, wherein the computer system is coupled to the SAN via a network interface, and wherein the SAN comprises a plurality of persistent caches;

the computer system causing the plurality of write operations to be sent from the system cache to the SAN;

the computer system receiving information from the SAN that indicates amounts of available memory within at least first and second ones of the plurality of persistent caches, wherein the at least first and second persistent caches are in different physical devices; and

in response to determining that the received information is indicative of a violation of a write caching policy, the computer system changing one or more latency parameters of the system cache to decrease a rate at which first and second sets of one or more write operations are provided from the computer system to the SAN, wherein the first set of write operations includes one or more target addresses corresponding to the first persistent cache, and wherein the second set of write operations includes one or more target addresses corresponding to the second persistent cache.

2. The method of claim 1 , wherein the violation is based on a current state of the computer system.

3. The method of claim 1 , wherein the computer system includes a plurality of computer servers.

4. The method of claim 1 , further comprising the computer system sending a plurality of polling messages to the first and second persistent caches, wherein said receiving information from the SAN is in response to sending the plurality of polling messages.

5. The method of claim 4 , wherein a first one of the plurality of polling messages destined for the first persistent cache is specific to a first type of storage device, and wherein a second one of the plurality of polling messages destined for the second persistent cache is specific to a second type of storage device.

6. The method of claim 1 , wherein the violation of the write caching policy is indicative of a seizure in the SAN.

7. The method of claim 1 , wherein the information received from the SAN includes one or more of the following:

information regarding a current status of write operations pending in at least one of the first or second persistent caches; and

historical information regarding past write operations to at least one of the first or second persistent caches.

8. The method of claim 1 , further including:

the computer system causing an amount of memory allocated to the system cache to be changed.

9. The method of claim 1 , further including:

the computer system assessing a degree of certainty of the violation, wherein the violation is based on a potential future state.

10. A non-transitory computer readable medium including program instructions that are executable by a computer system to cause the computer system to:

receive a plurality of write operations directed to a storage area network (SAN) via a system cache implemented in a memory of the computer system, wherein the write operations are issued by an application running on the computer system, wherein the computer system is coupled to the SAN via a network connection, and wherein the SAN comprises the plurality of persistent caches, each of which is configured to buffer write operations destined for a corresponding one of a plurality of storage arrays;

the computer system causing the plurality of write operations to be sent to the at least first and second persistent caches;

receive information from the SAN via the network connection that indicates amounts of available memory within at least the first and second ones of the plurality of persistent caches, wherein the at least first and second persistent caches are in different physical devices; and

in response to determining the received information from the SAN is indicative of a violation of a write caching policy, change one or more latency parameters of the system cache to decrease a rate at which first and second sets of one or more write operations are provided from the computer system to the SAN, wherein the first set of write operations includes one or more target addresses corresponding to the first persistent cache, and wherein the second set of write operations includes one or more target addresses corresponding to the second persistent cache.

11. The computer readable medium of claim 10 , wherein the program instructions are executable to cause the computer system to adjust a first latency parameter and a second latency parameter in response to the received information, wherein the first latency parameter corresponds to a first managed volume configured to receive write operations from the first persistent cache and wherein the second latency parameter corresponds to a second managed volume configured to receive write operations from the second persistent cache.

12. The computer readable medium of claim 10 , wherein the program instructions are executable to further cause the computer system to:

change the write caching policy in response to the violation of the write caching policy.

13. The computer readable medium of claim 10 , wherein the program instructions are executable to further cause the computer system to allocate additional memory to the system cache for buffering write operations.

14. The computer readable medium of claim 10 , wherein the write caching policy is configured according to storage requirements of the application.

15. A computer system, comprising:

a system cache;

a processor; and

a memory having stored therein program instructions executable to cause the computer system to:

execute an application configured to issue write operations to a storage area network (SAN), wherein the write operations issued by the application are forwarded to the SAN by an operating system of the computer system via the system cache, wherein the SAN comprises a plurality of persistent caches, each of which is configured to buffer write operations destined for a corresponding one of a plurality of storage arrays;

cause the issued write operations to be forwarded from the system cache to the SAN;

receive write operation information from the SAN, wherein the write operation information includes information specifying amounts of available memory within at least first and second ones of the plurality of persistent caches, wherein the first and second persistent caches are in different physical devices; and

in response to a determination that the received write operation information is indicative of a violation of a write caching policy, change one or more latency parameters of the system cache to decrease a rate at which first and second sets of one or more write operations are provided from the computer system to the SAN, wherein the first set of write operations includes one or more target addresses corresponding to the first persistent cache, and wherein the second set of write operations includes one or more target addresses corresponding to the second persistent cache.

16. The system of claim 15 , wherein the violation is indicative of a future state of the SAN.

17. The system of claim 15 , wherein determining that the received write operation information is indicative of a violation includes determining whether one or more rules of the write caching policy are violated, wherein determining whether one or more rules are violated is based at least in part on a plurality of parameters affecting the operation of the system cache.

18. The system of claim 17 , wherein the memory further includes program instructions executable by the processor to cause the computer system to change the write caching policy based at least in part on altered values for one or more of the plurality of parameters.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Dec 16, 2024
From: ACQUIOM AGENCY SERVICES LLC, AS COLLATERAL AGENT
To: VERITAS TECHNOLOGIES LLC (F/K/A VERITAS US IP HOLDINGS LLC)
Reel/Frame 069712/0090 →
ASSIGNMENT OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Nov 25, 2024
From: BANK OF AMERICA, N.A., AS ASSIGNOR
To: ACQUIOM AGENCY SERVICES LLC, AS ASSIGNEE
Reel/Frame 069440/0084 →
TERMINATION AND RELEASE OF SECURITY IN PATENTS AT R/F 037891/0726 Recorded Nov 30, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: VERITAS US IP HOLDINGS, LLC
Reel/Frame 054535/0814 →
MERGER AND CHANGE OF NAME Recorded Apr 18, 2016
From: VERITAS US IP HOLDINGS LLC; VERITAS TECHNOLOGIES LLC
To: VERITAS TECHNOLOGIES LLC
Reel/Frame 038455/0752 →
SECURITY INTEREST Recorded Feb 23, 2016
From: VERITAS US IP HOLDINGS LLC
To: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 037891/0726 →
SECURITY INTEREST Recorded Feb 23, 2016
From: VERITAS US IP HOLDINGS LLC
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037891/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: SYMANTEC CORPORATION
To: VERITAS US IP HOLDINGS LLC
Reel/Frame 037697/0412 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 019872 FRAME 979. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNEE IS SYMANTEC OPERATING CORPORATION. Recorded Mar 5, 2012
From: VERITAS OPERATING CORPORATION
To: SYMANTEC OPERATING CORPORATION
Reel/Frame 027819/0462 →
CHANGE OF NAME Recorded Sep 26, 2007
From: VERITAS OPERATING CORPORATION
To: SYMANTEC CORPORATION
Reel/Frame 019872/0979 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2006
From: NAGLER, JIM; BALAN, RAMESH
To: VERITAS OPERATING CORPORATION
Reel/Frame 018729/0568 →