Method and apparatus to program both sides of a non-volatile static random access memory
A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.
1. A method for programming a first and second tri-gate structure in a non-volatile SRAM cell having a volatile portion and a non-volatile portion, each tri-gate structure in said non-volatile portion having a recall transistor, a store transistor and a SONOS transistor, said volatile portion having an SRAM cell comprising a word line, a node supplying power to said SRAM cell and a bit line pair with a first bit line and a second bit line, said method comprising:
erasing said first and second SONOS transistors associated with said non-volatile portion of said SRAM cell;
grounding said first bit line and said second bit line;
grounding said node supplying power to said SRAM cell;
applying a voltage to said word line sufficient to turn the word line to an active state so as to discharge said internal data nodes of said SRAM cell to ground;
applying a voltage to each store transistor in said first and second tri-gate structure sufficient to turn each store transistor on; and
applying a programming pulse and programming voltage to each SONOS transistor in said first and second tri-gate structure to program said tri-gate structure in said non-volatile portion.
2. The method of claim 1 wherein said grounding of said first and second bit line further comprises grounding said first bit line of said bit line pair independent of said second bit line of said bit line pair using an array reset circuit.
3. A method for programming a first and second tri-gate structure in a non-volatile SRAM cell having a volatile portion and a non-volatile portion, each tri-gate structure in said non-volatile portion having a recall transistor, a store transistor and a SONOS transistor, said volatile portion having an SRAM cell comprising a word line, a node supplying power to said SRAM cell and a bit line pair with a first bit line and a second bit line, said method comprising:
erasing said first and second SONOS transistors associated with said non-volatile portion of said SRAM cell;
isolating said volatile portion from said non-volatile portion by turning off each store transistor in said first and second tri-gate structure;
applying power to each recall transistor in said first and second tri-gate structure sufficient to turn said each recall transistor on; and
applying a programming pulse and programming voltage to each SONOS transistor in said first and second tri-gate structure to program said tri-gate structure in said non-volatile portion.