Method of manufacture of a semiconductor integrated circuit device including a plurality of columnar laminates having different spacing in different directions
View Patent ↗For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O 3 -TEOS) having good coverage is disposed over columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.
1. A manufacturing method of a semiconductor integrated circuit device, comprising the steps of:
(a) forming a first columnar laminate, a second columnar laminate and a third columnar laminate over a semiconductor substrate;
(b) forming first insulating films over side walls of the first, the second and the third columnar laminates;
(c) forming conductive films over the side walls of the first, the second and the third columnar laminates via the first insulating films;
(d) forming a second insulating film to cover the conductive films, the first columnar laminate, the second columnar laminate and the third columnar laminate; and
(e) forming a third insulating film over the second insulating film;
wherein the second columnar laminate is adjusted to the first columnar laminate in a first direction,
wherein the third columnar laminate is adjusted to the first columnar laminate in a second direction being perpendicular to the first direction,
wherein a second distance between the first columnar laminate and the third columnar laminate is wider than a first distance between the first columnar laminate and the second columnar laminate,
wherein the second insulating film has a thickness enough to fill a space of the first distance and but not enough to fill a space of the second distance, and
wherein the third insulating film has a thickness enough to fill a space of the second distance.
2. A manufacturing method of a semiconductor integrated circuit device according to claim 1 , further comprising the steps of:
(g) before the step (a), forming a MISFET on the semiconductor substrate.
3. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein the second insulating film is comprised of a silicon oxide film and the step (d) is carried out by chemical vapor deposition using tetraethoxysilane as a raw material.
4. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein the second insulating film is comprised of a silicon oxide film and the step (d) is carried out by chemical vapor deposition using tetraethoxysilane and ozone (O3) as raw materials.
5. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein the third insulating film is comprised of a silicon oxide film and the step (f) is carried out in a plasma atmosphere having a plasma density of 101/cm2 or greater.
6. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein the first distance is 150 nm or less and the second distance is 500 nm or greater.