Memory having a dummy bitline for timing control
View Patent ↗A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations.
1. A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, the memory comprising:
a plurality of sense amplifiers coupled to the at least one memory array block;
at least one bit line comprising bitcells, wherein the N wordlines are used to select the bitcells;
at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N; and
a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pulldown transistors coupled to a sense circuit for generating a sense trigger signal used to enable the plurality of sense amplifiers, wherein each of the M dummy bitcells of the at least one dummy bitline includes pass gates that are negated such that none of the M dummy bitcells is selected using a dummy wordline.
2. The memory of claim 1 , wherein the at least one memory array block comprises a first memory array and a second memory array and wherein the at least one dummy bitline is located adjacent to at least one of the first memory array and the second memory array.
3. The memory of claim 1 further comprising a local control circuit for generating a clock signal for triggering the timing circuit and at least one of the N wordlines.
4. The memory of claim 1 , wherein the sense trigger signal is generated based on at least a load characteristic of the at least one dummy bitline.
5. The memory of claim 1 , wherein the timing circuit further comprises a plurality of stacks of pulldown transistors, wherein the at least one stack of pulldown transistors is selected from the plurality of stacks of pulldown transistors in response to a stack selection signal.
6. The memory of claim 5 , wherein pulldown transistors within a specific stack of pulldown transistors have same size.
7. The method of claim 6 , wherein the pulldown transistors vary in size from one stack of pulldown transistors to another stack of pulldown transistors.
8. The memory of claim 1 further comprising a plurality of dummy bitlines, wherein the timing circuit is coupled to the plurality of dummy bitlines and wherein each of the plurality of bitlines comprises M dummy bitcells, wherein M is equal to N.
9. A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, the memory comprising:
a plurality of sense amplifiers coupled to the at least one memory array block;
at least one bit line comprising bitcells, wherein the N wordlines are used to select the bitcells;
at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N; and
a timing circuit coupled to the at least one dummy bitline forming a node, wherein the timing circuit comprises at least one stack of pulldown transistors coupled to a sense circuit for generating a local reset signal used to precharge the node, wherein the local reset signal is generated based on at least a load characteristic of the at least one dummy bitline,
wherein each of the M dummy bitcells of the at least one dummy bitline includes pass gates that are negated such that none of the M dummy bitcells is selected using a dummy wordline.
10. The memory of claim 9 , wherein the at least one memory array block comprises a first memory array and a second memory array and wherein the at least one dummy bitline is located adjacent to at least one of the first memory array and the second memory array.
11. The memory of claim 10 , wherein the at least one dummy bitline is located nearest to a plurality of wordline drivers coupled to the at least one memory array block.
12. The memory of claim 9 further comprising a local control circuit for generating a clock signal for triggering the timing circuit and at least one of the N wordlines.
13. The memory of claim 9 , wherein the timing circuit further comprises a plurality of stacks of pulldown transistors, wherein the at least one stack of pulldown transistors is selected from the plurality of stacks of pulldown transistors in response to a stack selection signal.
14. The memory of claim 13 , wherein pulldown transistors within a specific stack of pulldown transistors have same size.
15. The memory of claim 14 , wherein the pulldown transistors vary in size from one stack of pulldown transistors to another stack of pulldown transistors.
16. A method for operating a memory comprising at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, the memory further comprising a plurality of sense amplifiers coupled to the at least one memory array block, at least one bit line comprising bitcells, wherein the N wordlines are used to select the bitcells, at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N, and a timing circuit, the method comprising:
receiving a read or write operation signal;
using the timing circuit, generating a sense trigger signal used to enable the plurality of sense amplifiers, wherein a timing of generation of the sense trigger signal is a function of at least a capacitive load associated with the at least one dummy bitline, and wherein the timing of generation of the sense trigger signal is independent of a capacitive load associated with a dummy wordline, and wherein each of the M dummy bitcells of the at least one dummy bitline includes pass gates that are negated such that none of the M dummy bitcells is selected using the dummy wordline.
17. The method of claim 16 , wherein a change in the at least the capacitive load of the at least one dummy bitline tracks a change in a size of the memory.
18. The method of claim 16 , wherein the timing circuit comprises a plurality of stacks of pulldown transistors and the method further comprising:
selecting one of the plurality of stacks of pulldown transistors in response to a receipt of a stack selection signal.
19. The method of claim 16 , wherein a coupling of the timing circuit and the at least one dummy bitline forms a node, the method further comprising:
generating a local reset signal used to precharge the node.
20. The method of claim 19 , wherein the memory further comprises a sense latch, the method further comprising:
using the local reset signal:
to reset control logic associated with the memory;
to terminate the read or write operation; and
to reset the sense latch.