IP Library Granted Patent US 8,786,360
Granted Patent B2
US 8,786,360 · App. 11/679,364 · Granted Jul 22, 2014

Circuit and method for fast switching of a current mirror with large MOSFET size

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,786,360
App. No.
11/679,364
Granted
Jul 22, 2014
Kind
B2
Abstract

The present invention discloses a fast switching current mirror circuit and method for generating fast switching current. The circuit and method for fast switching of a current mirror with large MOSFET size will save space and current consumption.

Claims (29)

1. A circuit for providing a switched current comprising:

a first current mirror having a power terminal coupled to a source of supply voltage, an input, and an output;

a second current mirror having an input for receiving an input current, a first output coupled to the output of the first current mirror, a second output coupled to the input of the first current mirror, and a power terminal coupled to ground;

a draining module having an input coupled to the output of the first current mirror, a first output coupled to the input of the first current mirror, and a second output coupled to ground; and

an MOS output transistor having a gate coupled to the input of the first current mirror through a first switch and coupled to the source of supply voltage through a second switch, a first current terminal coupled to the source of supply voltage, and a second current terminal for providing the switched current.

2. The circuit of claim 1 wherein the first current mirror comprises a PMOS current mirror.

3. The circuit of claim 1 wherein the first current mirror comprises a first transistor one-thousandth the size of the output transistor.

4. The circuit of claim 3 wherein the first current mirror comprises a second transistor one-thousandth the size of the output transistor.

5. The circuit of claim 1 wherein the second current mirror comprises an NMOS current mirror.

6. The circuit of claim 1 wherein the draining module comprises:

an inverter having an input coupled to the input of the draining module, and an output; and

a transistor having a gate coupled to the output of the inverter, a first current output coupled to the first output of the draining module, and a second current output coupled to the second output of the draining module.

7. The circuit of claim 6 wherein the transistor comprises an NMOS transistor.

8. The circuit of claim 1 wherein the input current is equal to 50 μA.

9. The circuit of claim 1 wherein the switched current is switched to 50 mA.

10. The circuit of claim 1 wherein the first current mirror comprises a unity gain current mirror.

11. The circuit of claim 1 wherein the second current mirror comprises a unity gain current mirror.

12. A circuit for providing a switched current comprising:

a first current mirror;

a second current mirror for receiving an input current having first and second outputs coupled to the first current mirror;

an inverter having an input coupled to the first output of the second current mirror, and an output;

a first transistor having a gate coupled to the output of the inverter, a drain coupled to the second output of the second current mirror, and a source coupled to ground; and

a second transistor having a gate coupled to an input of the first current mirror through a first switch and coupled to a source of supply voltage through a second switch, a source coupled to the source of supply voltage, and a drain for providing the switched current, wherein the second transistor comprises an MOS transistor.

13. A circuit for providing a switched current comprising:

a first current mirror;

a second current mirror for receiving an input current having first and second outputs coupled to the first current mirror;

an inverter having an input coupled to the first output of the second current mirror, and an output;

a draining transistor having a gate coupled to the output of the inverter, a drain coupled to the second output of the second current mirror, and a source coupled to ground; and

a switched MOS output transistor having a gate coupled to an input of the first current mirror, a source coupled to a source of supply voltage, and a drain for providing the switched current.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS ASIA PACIFIC PTE LTD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068434/0215 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2007
From: ANG, JUSTIN
To: STMICROELECTRONICS ASIA PACIFIC PTE, LTD.
Reel/Frame 018937/0620 →