Apparatus for efficient streaming data access on reconfigurable hardware and method for automatic generation thereof

1. A method for updating a content addressable memory (CAM) comprising a memory having a first port configured to white a 1-bit data to the memory and a second port configured to access the memory to read and write N-bit data, where N is greater than one, the method comprising:

writing an N-bit zero data word to the second port at a first address A 2 to erase N bits of the memory at address A 2 ;

combining the first address A 2 with a data value A 0 to form a second address A 1 ; and

writing a value 1 to the first data port at the address A 1 , to set bit of memory at the second address A 1 ,

wherein reading the second port at the first address A 2 will produce an N-bit data word having value 1 at bit position A 0 and zero at all other bit positions.

2. A method in accordance with claim 1 , wherein A 0 is a Y-bit value and N≦2 Y and wherein the first port is configured to store 1-bit data at up to 2 X+Y locations addressed by an (X+Y)-bit address and the second port is configured to store 2 Y -bit data at up to 2 X locations addressed by an X-bit address.

3. A method in accordance with claim 1 , wherein the data value A 0 comprises an external memory address and the address A 2 comprises a memory bus access tag associated with a request to access an external memory at the address A 0 .

4. A method in accordance with claim 3 , further comprising:

reading Port B at an address B 2 to retrieve an N-bit data word B 3 , having a value 1 in bit B 0 and zeroes at all other bit positions; and

associating the received data value with a request to access the external memory at address B 0 .

5. A method in accordance with claim 1 , wherein the memory comprises a plurality of sub-blocks and wherein writing an N-bit zero data word to the second port at the first address A 2 to erase N bits of the memory at address A 2 comprises:

selecting at least two sub-block of memory of the plurality of sub-blocks dependent upon the address A 2 ;

selecting an address in the least two selected sub-block of memory dependent upon the address A 2 ; and

writing zero to each of the least two selected sub-block at the selected address.

6. A method in accordance with claim 1 , wherein the memory comprises a plurality of sub-blocks and wherein writing a value 1 to the first data port at the address A 1 comprises:

selecting at a sub-block of memory of the plurality of sub-blocks dependent upon the address A 1 and the data value A 0 ;

selecting an address in the selected sub-block of memory dependent upon the address A 1 and the data value A 0 ; and

writing a value 1 to the selected sub-block at the selected address.

7. A method in accordance with claim 1 , wherein the memory comprises a plurality of sub-blocks, the method further comprising:

selecting at least two sub-blocks of memory of the plurality of sub-blocks dependent upon the address A 2 ;

selecting an address in the least two selected sub-block of memory dependent upon the address A 2 ;

reading the at least two selected sub-block of memory at the selected address to obtain at least two intermediate words; and

combining the at least two intermediate words to form an N-bit data word.

8. A method in accordance with claim 1 , wherein the memories comprise random access memories in a field programmable gate array (FPGA).

9. A content addressable memory (CAM) comprising:

a memory having a first port operable to write 1-bit data to the memory, and a second port operable to write N-bit data from the memory, where N is greater than 1, and further operable to read N-bit data from the memory; and

a control module operable to update the N-bit data in the memory at a first address A 2 by:

writing an N-bit zero data word to the second port at the first address A 2 ;

combining the first address A 2 with a data value A 0 to form a second address A 1 ; and

writing a value 1 to the first data port at the second address A 1 , the control module further operable to search the memory by:

reading the second port at a third address B 2 to retrieve a N-bit data value B 3 ;

associating the value B 0 with the value B 2 if the value B 3 has value 1 at bit position B 0 and zeros at all other bit positions; and

determining the value B 2 to be unmatched if the value B 3 has value 0 at all bit positions.

10. A content addressable memory in accordance with claim 9 , wherein A 0 is a Y-bit value and N≦2 Y and wherein the first port is configured to store 1-bit data at up to 2 X+Y locations addressed by an (X+Y)-bit address and the second port is configured to store N-bit data at up to 2 X locations addressed by an X-bit address.

11. A content addressable memory in accordance with claim 9 , wherein the memory comprises a plurality of sub-blocks of memory each operable to stored data of width less than N-bits, and wherein writing an N-bit zero data word to the second port at the first address A 2 comprises writing zero data to each of the plurality of sub-blocks of memory at the first address A 2 .

12. A content addressable memory in accordance with claim 9 , wherein the memory comprises a plurality of sub-blocks of memory each operable to stored data of width N-bits, and wherein writing an N-bit zero data word to the second port at the first address A 2 comprises:

selecting a sub-block of memory of the plurality of sub-blocks of memory dependent upon the address A 2 ;

selecting an address in the selected sub-block of memory dependent upon the address A 2 ; and

writing zero to the selected sub-block of memory at the selected address.

13. A content addressable memory in accordance with claim 9 , wherein the memory comprises a plurality of sub-blocks of memory and wherein writing a value 1 to the first data port at the second address A 1 comprises:

selecting a cub-block of memory of the plurality of sub-blocks of memory dependent upon the address A 1 ;

selecting an address in the selected sub-block of memory dependent upon the address A 1 ; and

writing a value 1 to the selected sub-block of memory at the selected address.

14. A content addressable memory in accordance with claim 9 , wherein the memory comprises at least one block Random Access Memory (RAM).

15. A content addressable memory in accordance with claim 9 , wherein the control module comprises a reconfigurable logic circuit.

16. A content addressable memory in accordance with claim 9 , wherein the control module comprises a Field Programmable Gate Array (FPGA).