Integrated circuit with testable clock circuits
View Patent ↗An integrated circuit ( 1 ) that comprises an internal clock circuit ( 12 ) with a clock output for clocking functional circuits ( 10 ) of the integrated circuit ( 1 ). The integrated circuit is provided with a counter circuit ( 16 ) and a state holding circuit ( 18 ) for use during testing. The integrated circuit is switched to a test mode and a start of a test time interval is signalled. Clock pulses from the internal clock circuit 12 are counted from the start of the test time interval and the state holding circuit ( 18 ) is locked into a predetermined state if the internal clock circuit has produced more than a predetermined number of clock pulses from the start of the test time interval. Information about whether the state holding circuit ( 18 ) has reached the predetermined state in the test time interval is read from the integrated circuit ( 1 ) and the information is used by a test evaluation apparatus ( 2 ) to accept or reject the integrated circuit ( 1 ).
1. A testable integrated circuit, comprising
a test interface circuit arranged to switch the integrated circuit between a functional operating mode and a test mode
an internal clock circuit with a clock output for clocking functional circuits of the integrated circuit at least in the functional operating mode;
a test circuit comprising
a pulse counting circuit with a clock input coupled to the clock output;
a state holding circuit that is coupled to the pulse counting circuit or is part of the pulse counting circuit, arranged so that the state holding circuit will lock into a predetermined state when a threshold number of clock pulses has bean applied to the clock input following a start of a time interval defined by the test interface circuit;
the test interface circuit being coupled to the state holding circuit for reading out information from the integrated circuit about whether the state holding circuit has reached the predetermined state before the end of the time interval.
2. A testable integrated circuit according to claim 1 , wherein the clock circuit is one of a plurality of clock circuits, each of the clock circuits having a respective clock output for clocking the functional circuits, the integrated circuit comprising a multiplexing circuit coupled between the clock outputs of the clock circuits and the clock input of the pulse counting circuit, the multiplexing circuit ( 30 ) having a control input coupled to the test interface circuit, for controlling which of the clock circuits the multiplexing circuit will couple to the clock input of the pulse counting circuit, under control of a test command.
3. A testable integrated circuit according to claim 1 , wherein the test interface circuit comprises a pin multiplexing circuit with an input coupled to an output of the state holding circuit and an output coupled to an external terminal of the integrated circuit.
4. A method of testing an integrated circuit that comprises an internal clock circuit with a clock output for clocking functional circuits of the integrated circuit at least in a functional operating mode, the method comprising
switching the integrated circuit to a test mode and signalling a start of a test time interval;
counting clock pulses from the internal clock circuit 12 from the start of the test time interval;
locking a state holding circuit into a predetermined state if the internal clock circuit has produced more than a predetermined number of clock pulses from the start of the test time interval;
reading information about whether the state holding circuit has reached the predetermined state in the test time interval;
supplying said information to a test evaluation apparatus to accept or reject the integrated circuit dependent on said information.
5. A method according to claim 4 , wherein the integrated circuit comprises a plurality of internal clock circuits, each with a respective clock output for clocking the functional circuits, the method comprising coupling clock signals from respective ones of the clock outputs successively to the state holding circuit, through a counting circuit, each for locking the state holding circuit into the predetermined state if the respective one of the clock output has produced more than a predetermined number of clock pulses from the start of a respective test time interval.