Adiabatic CMOS design
An integrated circuit comprising a plurality of CMOS modules ( 10 ) connected in series with each other, each module ( 10 ) being connected between first and second reference lines (Vdd, Vss). A first transistor ( 54 ) is provided between at least one of the modules ( 10 ) and the first reference line (Vdd) and a second transistor ( 52 ) is provided between one of the modules ( 10 ) and the second reference line (Vss) and capacitors (C 25 , C 26 ) are provided in parallel with the transistors ( 52, 54 ) such that they are driven as current sources (I 1 , I 2 ). As a result power dissipation and leakage current is reduced.
1. An adiabatic circuit comprising:
a first reference line;
a second reference line;
a CMOS module connected between the first reference line and the second reference line,
a first transistor connected between the CMOS module and the first reference line;
a second transistor connected between the CMOS module and the second reference line;
a first capacitive circuit connected in parallel with the first transistor, and
a second capacitive circuit connected in parallel with the second transistor, wherein the first and second transistors are configured and arranged to operate as first and second respective current sources that are configured to establish a fixed voltage across the respective first and second capacitive circuits.
2. An adiabatic circuit according to claim 1 , wherein said first and second capacitive circuits comprise respective trench capacitors.
3. An adiabatic circuit according to claim 1 , wherein said first and second capacitive circuits comprise off-chip capacitors.
4. An adiabatic circuit according to claim 1 , further comprising a charge pump for directing charge stored in said first and second capacitive circuits to a supply.
5. An adiabatic circuit according to claim 4 , wherein said charge pump is arranged and configured to direct charge from said supply to said first and second capacitive circuits.
6. A method of fabricating a CMOS module, the method comprising:
providing a CMOS circuit on a substrate,
connecting said CMOS circuit between a first reference line and a second reference line via respective first and second transistors being provided in series with said first and second reference lines, and
providing first capacitive circuit in parallel with said first transistor and second capacitive circuit in parallel with said second transistor wherein said first and second transistors operate as first and second respective current sources that are configured to establish a fixed voltage across the respective first and second capacitive circuits.
7. An integrated circuit comprising
a first reference line;
a second reference line;
a plurality of CMOS circuits connected in series with each other, said CMOS circuits being connected between the first reference line and the second reference line;
a first transistor connected between at least one of said CMOS circuits and said first reference line;
a second transistor connected between at least one of said CMOS circuits and said second reference line;
a first capacitive circuit connected in parallel with said first transistor; and
a second capacitive circuit connected in parallel with said second transistor,
wherein said first and second transistors are configured and arranged to operate as respective current sources that are configured to establish a fixed voltage across the respective first and second capacitive circuits.
8. An integrated circuit according to claim 7 , comprising a supply and a charge pump for directing charge stored in said first and second capacitive circuits to said supply.
9. An integrated circuit according to claim 8 , comprising a decoupling capacitive circuit in series with said supply through which said charge is directed by said charge pump.
10. An integrated circuit according to claim 9 , wherein said decoupling capacitive circuit comprises one or more relatively large trench capacitors.
11. A method of fabricating an integrated circuit, the method comprising:
forming a plurality of CMOS circuits in a substrate,
connecting said CMOS circuits in series with each other,
connecting each CMOS circuit between a first reference line and a second reference line,
providing a first transistor between at least one of said CMOS circuits and said first reference line,
providing a second transistor between at least one of said CMOS circuits and said second reference line,
providing a first capacitive circuit in parallel with said first transistor and
providing a second capacitive circuit in parallel with said second transistor wherein said first and second transistors operate as first and second respective current sources that are configured to establish a fixed voltage across the respective first and second capacitive circuits.
12. The method of claim 11 , wherein the first transistor operates as a current source that directs current in a direction from the CMOS circuits to the first reference line and wherein the second transistor operates as a current source that directs current in a direction from the CMOS circuits to the second reference line.
13. The circuit of claim 1 , wherein the first transistor operates as a current source that generates a current from the CMOS module to the first reference line, and wherein the second transistor operates as a current source that generates a current from the CMOS module to the second reference line.
14. The circuit of claim 1 , wherein the first transistor operates as a current source that generates a back bias voltage level across the first capacitive circuit and wherein the second transistor operates as a current source that generates a back bias voltage level across the second capacitive circuit.
15. The method of claim 11 , wherein the first transistor operates as a current source that generates a back bias voltage level across the first capacitive circuit and wherein the second transistor operates as a current source that generates a back bias voltage level across the second capacitive circuit.
16. The method of claim 6 , wherein the first and second transistors are configured and arranged to operate as current sources that create a back bias voltage level across the first capacitive circuit and the second capacitive circuit.
17. The circuit of claim 7 , wherein the first and second transistors are configured and arranged to generate a back bias voltage level across the first capacitive circuit and the second capacitive circuit.