IP Library Patent Application 11720820
Patent Application
App. No. 11/720,820

STREAMING MEMORY CONTROLLER

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
11/720,820
Abstract

A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The memory controller (SMC) comprises a first interface (PI), a streaming memory unit (SMU) and a second interface (MI). The first interface (PI) is used for connecting the memory controller (SMC) to the network (N) for receiving and transmitting data streams (ST 1 -ST 4 ). The streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (ST 1 -ST 4 ) between the network (N) and the memory (MEM). The streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (ST 1 -ST 4 ) and a buffer managing unit (BMU) for managing the temporarily storing of the data streams (ST 1 -ST 4 ) in the buffer (B). The second interlace (MI) is coupled to the streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM) in order to exchange data with the memory (MEM) in bursts. The streaming memory unit (SMU) is provided to implement network services of the network (N) onto the memory (MEM).

Claims (22)

1 . A memory controller (SMC) for coupling a memory (MEM) to a network (N) comprising:

a first interface (PI) for connecting the memory controller (SMC) to the network (N), the first interface (PI) being arranged for receiving and transmitting data streams; and

a streaming memory unit (SMU) coupled to the first interface (PI) for controlling data streams (ST 1 -ST 4 ) between the network (N) and the memory (MEM), said streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (ST 1 -ST 4 ), and a buffer managing unit (BMU) for managing a temporarily storing of data streams (ST 1 -ST 4 ) in the buffer (B),

a second interface (MI) coupled to a streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM), and for exchanging data with the memory (MEM) in bursts,

wherein said streaming memory unit (SMU) is arranged to implement network services of the network (N) onto the memory (MEM).

2 . A memory controller according to claim 1 , wherein the first interface (PI) is a PCI express interface.

3 . A memory controller according to claim 1 or 2 , wherein

the memory (MEM) is at least partly organized as FIFOs, and a stream identifier is associated to every data stream,

the stream memory unit (SMU) is arranged for controlling a data stream (ST 1 -ST 4 ) from/or to the network (N) by directing a particular data stream (ST 1 -ST 4 ) to a particular FIFO in the memory (MEM) according to the stream identifier of the data stream, and for arbitrating between the streams for access to the memory (MEM),

the second interface (MI) is arranged for exchanging a relatively course grained stream of data with the memory and a relatively fine grained stream of data with the network.

4 . A memory controller according to claim 3 , wherein the network (N) is a PCI-Express network, and a PCI-Express ID is used in the network (N) for addressing, wherein the first interface (PD is a PCI express interface, and wherein the streaming memory unit (SMU) is arranged for converting a PCI-express ID into a FIFO-memory address and a FIFO-memory address into a PCI-express ID.

5 . A memory controller according to claim 1 , wherein the first interface (PI) is adapted for traffic shaping of the data received from the memory (MEM) to comply with traffic rules of the network (N), and

wherein the second interface (MI) is adapted for traffic shaping of the data retrieved from the network (N) to comply with traffic rules of the memory (MEM).

6 . Method for coupling a memory (MEM) to a network (N) comprising the steps of:

receiving and transmitting data streams (ST 1 -ST 4 ) via a first interface (PI) for connecting a memory controller (SMC) to the network (N);

controlling the data streams (ST 1 -ST 4 ) between the network (N) and the memory (MEM) by a streaming memory unit (SMU);

temporarily storing at least part of the data streams (ST 1 -ST 4 ) in a buffer (B);

managing the temporarily storing of the data streams (ST 1 -ST 4 ) in a buffer (B);

connecting the streaming memory controller (SMC) to the memory (MEM) via a second interface (NI) and exchanging data with the memory (MEM) in bursts;

implementing network services of the network (N) onto the memory (MEM).

7 . Data processing system, comprising a network (N) having a plurality of processing units (P) and an interconnect means (IM) for coupling the processing units (P) and

a memory controller (SMC) for coupling the network (N) to a memory (MEM) according to one of the claims 1 to 5 .

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2010
From: BURCHARD, ARTUR; HEKSTRA-NOWACKA, EWA; HARMSZE, FRANCOISE J.; HAMER, PETER VAN DEN
To: NXP B.V .
Reel/Frame 024214/0112 →
DEED OF TRANSFER OF PATENTS Recorded Nov 25, 2009
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 023571/0580 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2009
From: BURCHARD, ARTUR TADEUSZ; HEKSTRA-NOWACKA, EWA; HARMSZE, FRANCOISE JENNETTE; HAMER, PETER
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 023173/0901 →