IP Library Granted Patent US 7,554,392
Granted Patent B2
US 7,554,392 · App. 11/739,355 · Granted Jun 30, 2009

Multiple output power mode amplifier

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Quick Facts
Patent No.
US 7,554,392
App. No.
11/739,355
Granted
Jun 30, 2009
Kind
B2
Abstract

A multi-mode power amplifier and an electronic device including the amplifier are described.

Claims (22)

1. A multiple power mode amplifier, comprising:

(a) an input impedance matching network having an input configured to receive an input signal;

(b) a first driver operably coupled to the input impedance matching network and configured to amplify the input signal and provide a first driver output signal therefrom;

(c) a first impedance matching network operably connected to the first driver and configured to receive the first driver output signal and provide a first impedance matching network output signal therefrom;

(d) a second driver operably coupled to the second impedance matching network and configured to amplify the first impedance matching network output signal and provide a second driver output signal therefrom;

(e) a second impedance matching network operably connected to the second driver and configured to receive the second driver output signal and provide a second impedance matching network output signal therefrom;

(f) a third impedance matching network operably connected to the second impedance matching network and configured to receive the second impedance matching network output signal and provide a third impedance matching network output signal therefrom;

(g) a power stage operably coupled to the third impedance matching network and configured to amplify the third impedance matching network output signal and provide a power stage output signal therefrom;

(h) a fourth impedance matching network operably connected to the power stage and configured to receive the power stage output signal and provide a fourth impedance matching network output signal therefrom;

(i) a fifth impedance matching network operably connected to the fourth impedance matching network and configured to receive the fourth impedance matching network output signal and provide a fifth impedance matching network output signal therefrom;

(j) an impedance transformation network operably coupled between a first node located between the second and third impedance matching networks and a second node located between the fourth and fifth impedance matching networks; and

(k) voltage control circuitry operably connected to the first driver, the second driver and the power stage, and configured to adjust quiescent (Q) currents corresponding to the first and second drivers, and to turn the power stage on and off;

wherein the power mode amplifier is further configured to operate in high-, mid- and low-power modes such that in a high-power mode the input signal traverses the input impedance matching network, the first driver, the first impedance matching network, the second driver, the second and third impedance matching networks, the power stage, and the fourth and fifth impedance matching networks while the power stage is turned on and Q-currents of the first and second drivers are set to a high level by the voltage control circuitry, in a mid-power mode the input signal traverses the input impedance matching network, the first driver, the first impedance matching network, the second driver, the second impedance matching network, the impedance transformation network, and the fifth impedance matching network while the power stage is turned off and Q-currents of the first and second drivers are set to a middle level by the voltage control circuitry, and in a low-power mode the input signal traverses the input impedance matching network, the first driver, the first impedance matching network, the second driver, the second impedance matching network, the impedance transformation network, and the fifth impedance matching network while the power stage is turned off and Q-currents of the first and second drivers are set to a low level by the voltage control circuitry.

2. The multiple power mode amplifier of claim 1 , wherein the amplifier includes no DC-DC converters or RF switches.

3. The multiple power mode amplifier of claim 1 , wherein in the high-power mode the first driver, the second driver and the power stage Q-currents are about 5 mA, about 20 mA and about 60 mA, respectively.

4. The multiple power mode amplifier of claim 1 , wherein in the mid-power mode the first driver, the second driver and the power stage Q-currents are about 4 mA, about 16 mA and about 0 mA, respectively.

5. The multiple power mode amplifier of claim 1 , wherein in the low-power mode the first driver, the second driver and the power stage Q-currents are about 3 mA, about 7 mA and about 0 mA, respectively.

6. The multiple power mode amplifier of claim 1 , wherein the fifth impedance matching network output signal provided by the amplifier is substantially linear.

7. The multiple power mode amplifier of claim 1 , wherein the voltage control circuitry comprises a Control Signal 1 (Vctrl 1 ) input and a Control Signal 2 (Vctrl 2 ) input.

8. The multiple power mode amplifier of claim 1 , wherein the amplifier is incorporated into one or a combination of one or more of: a mobile telephone; a personal digital assistant; a portable computer; a portable camera; a portable video player; a portable music player; and a portable gaming device.

9. The multiple power mode amplifier of claim 1 , wherein the amplifier is a power amplifier module (PAM).

10. The multiple power mode amplifier of claim 1 , wherein the amplifier is incorporated into a device comprising one or more of a display and an antenna.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030369/0703 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2008
From: HWA, JUNG SANG; MOON-SUK, JEON; KANG, KYUNG-TAL; HYUN, KIM JUNG
To: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
Reel/Frame 020347/0705 →