System and method for target device access arbitration using queuing devices
A system and method for slave-side arbitration includes a plurality of master devices, a target device, and an arbitrator for arbitrating access to the target device by the master devices. Queuing devices, such as FIFO buffers, are respectively associated with master devices and communicate information regarding retained target device access requests to the arbitrator. The information may be communicated to the arbitrator by sending it to the arbitrator, or may be provided as status information that is accessed by the arbitrator. The arbitrator uses an arbitration scheme and information regarding retained transaction requests to determine which master device should be granted access to the target device. The arbitration system and method can be used in an integrated circuit with multiple embedded processors, and can be implemented in a document processing system to improve overall system performance over conventional slave-side arbitration schemes.
1 . A system having multiple master devices that require access to a common target device, the system comprising:
a plurality of master devices including at least a first master device and a second master device;
a target device associated to the plurality of master devices, the target device being configured to fulfill transactions respectively requested by the plurality of master devices;
an arbitrator, in operative communication with the plurality of master devices and the target device, which arbitrates access to the target device in relation to the transactions respectively requested by the plurality of master devices;
a first queuing device in operative communication with the first master device and the arbitrator, the first queuing device being configured to receive transaction requests from the first master device and to communicate information regarding retained transaction requests to the arbitrator; and
a second queuing device in operative communication with the second master device and the arbitrator, the second queuing device being configured to receive transaction requests from the second master device and to communicate information regarding retained transaction requests to the arbitrator,
wherein the arbitrator arbitrates access to the target device based upon an arbitration scheme and the communicated information regarding retained transaction requests.
2 . The system according to claim 1 , wherein said first and second queuing devices are FIFO devices, and wherein said first FIFO device has a wait signal output that is fed back to the first master device, and said second FIFO device has a wait signal output that is fed back to the second master device.
3 . The system according to claim 1 , wherein the information regarding retained transaction requests comprises empty status information indicating that the queuing device is empty, and the arbitration scheme takes into account the empty status information respectively received from the first and second queuing devices.
4 . The system according to claim 1 , wherein the information regarding retained transaction requests comprises ready status information indicating that the queuing device has a retained transaction, and the arbitration scheme takes into account the ready status information respectively received from the first and second queuing devices.
5 . The system according to claim 1 , wherein the information regarding retained transaction requests comprises queue status information indicating the number of entries currently in the queuing device, and the arbitration scheme takes into account the queue status information respectively received from the first and second queuing devices.
6 . The system according to claim 1 , wherein the information regarding retained transaction requests comprises empty status information indicating that the queuing device is empty, ready status information indicating that the queuing device has a retained transaction, and queue status information indicating the number of entries currently in the queuing device, wherein the arbitration scheme takes into account the empty status, ready status and queue status information respectively received from the first and second queuing devices.
7 . The system according to claim 1 , further comprising a third master device and a third queuing device in operative communication with the third master device and the arbitrator.
8 . The system according to claim 1 , wherein the requested transactions are read and write operations and the arbitrator is operable to determine which of the plurality of master devices are granted access to the target device to perform read or write operations.
9 . The system according to claim 8 , wherein the first and second queuing devices each retain output data that comprises at least one of address, command, and write data to be passed to said target device when access is granted.
10 . The system according to claim 1 , wherein the first and second queuing devices are FIFO devices, and wherein the depth of each of the first and second FIFO devices is greater than a number of system clock cycles required to implement an arbitration function of the arbitrator.
11 . An integrated circuit, comprising:
a plurality of processors including at least a first processor and a second processor;
a memory interface device associated to the plurality of processors, the memory interface being configured to fulfill transactions respectively requested by the plurality of processors;
an arbitrator, in operative communication with the memory interface device, which arbitrates access to the memory interface device in relation to the transactions respectively requested by the plurality of processors;
a first queuing device in operative communication with the first processor and the arbitrator, the first queuing device being configured to receive transaction requests from the first processor and to communicate information regarding retained transaction requests to the arbitrator; and
a second queuing device in operative communication with the second processor and the arbitrator, the second queuing device being configured to receive transaction requests from the second processor and to communicate information regarding retained transaction requests to the arbitrator,
wherein the arbitrator arbitrates access to the memory interface device based upon an arbitration scheme and the communicated information regarding retained transaction requests.
12 . The integrated circuit according to claim 11 , wherein said integrated circuit is a multi-core processor, and said first and second processors are embedded in said integrated circuit.
13 . A document processing system, comprising:
a plurality of master devices including at least a first master device and a second master device;
a target device associated to the plurality of master devices, the target device being configured to fulfill transactions respectively requested by the plurality of master devices;
an arbitrator, in operative communication with the plurality of master devices and the target device, which arbitrates access to the target device in relation to the transactions respectively requested by the plurality of master devices;
a first queuing device in operative communication with the first master device and the arbitrator, the first queuing device being configured to receive transaction requests from the first master device and to communicate information regarding retained transaction requests to the arbitrator; and
a second queuing device in operative communication with the second master device and the arbitrator, the second queuing device being configured to receive transaction requests from the second master device and to communicate information regarding retained transaction requests to the arbitrator
wherein the arbitrator arbitrates access to the target device based upon an arbitration scheme and the communicated information regarding retained transaction requests.
14 . The document processing system according to claim 13 , wherein the first master device is an image lift device, and the second master device is a host processor device.
15 . The document processing system according to claim 13 , wherein the plurality of master devices respectively comprise host processor devices selected from the group consisting of: an image capture processor for storing raw camera data after detection by an image lift device, a top/bottom statistics processor for storing location of the top and bottom of each scan line of incoming video, a histogram statistics processor for storing document histogram data collected from the image lift device, a compressor input processor for reading document pixel data to be compressed, and a compressed output processor for storing compressed document data.
16 . The document processing system according to claim 13 , wherein the first and second queuing devices are integrated within a field-programmable gate array.
17 . The document processing system according to claim 13 , wherein the information regarding retained transaction requests comprises empty status information indicating that the queuing device is empty, and the arbitration scheme takes into account the empty status information respectively received from the first and second queuing devices.
18 . The document processing system according to claim 13 , wherein the information regarding retained transaction requests comprises ready status information indicating that the queuing device has a retained transaction, and the arbitration scheme takes into account the ready status information respectively received from the first and second queuing devices.
19 . The document processing system according to claim 13 , wherein the information regarding retained transaction requests comprises empty status information indicating that the queuing device is empty, ready status information indicating that the queuing device has a retained transaction, and queue status information indicating the number of entries currently in the queuing device, wherein the arbitration scheme takes into account the empty status, ready status and queue status information respectively received from the first and second queuing devices.
20 . The document processing system according to claim 13 , wherein the requested transactions are read and write operations and the arbitrator is operable to determine which of the plurality of master devices are granted access to the target device to perform read or write operations.
21 . A method for arbitrating target system access in a system where at least one target device is configured to fulfill transactions respectively requested by a plurality of master devices including at least a first master device and a second target device, the method comprising:
receiving in a first queuing device transaction requests from the first master device and communicating information regarding retained transaction requests to an arbitrator;
receiving in a second queuing device transaction requests from the second master device and communicating information regarding retained transaction requests to the arbitrator; and
arbitrating access to the target device in relation to transactions respectively requested by the plurality of master devices based upon an arbitration scheme and the communicated information regarding retained transaction requests.
22 . The method of claim 21 , wherein the information regarding retained transaction requests comprises empty status information indicating that the queuing device is empty, and the arbitration scheme takes into account the empty status information respectively received from the first and second queuing devices.
23 . The method of claim 21 , wherein the information regarding retained transaction requests comprises ready status information indicating that the queuing device has a retained transaction, and the arbitration scheme takes into account the ready status information respectively received from the first and second queuing devices.
24 . The method of claim 21 , wherein the information regarding retained transaction requests comprises empty status information indicating that the queuing device is empty, ready status information indicating that the queuing device has a retained transaction, and queue status information indicating the number of entries currently in the queuing device, wherein the arbitration scheme takes into account the empty status, ready status and queue status information respectively received from the first and second queuing devices.
25 . The method of claim 21 , wherein the requested transactions are read and write operations and the arbitrator scheme determines which of the plurality of master devices are granted access to the target device to perform read or write operations.
26 . A computer program product, for arbitrating target system access in a system where at least one target device is configured to fulfill transactions respectively requested by a plurality of master devices including at least a first master device and a second target device, the computer program product having instructions stored on a computer readable medium that when executed provide target system arbitration comprising:
receiving in a first queuing device transaction requests from the first master device and communicating information regarding retained transaction requests to an arbitrator;
receiving in a second queuing device transaction requests from the second master device and communicating information regarding retained transaction requests to the arbitrator; and
arbitrating access to the target device in relation to transactions respectively requested by the plurality of master devices based upon an arbitration scheme and the communicated information regarding retained transaction requests.
27 . The computer program product of claims 26 , wherein the information regarding retained transaction requests comprises empty status information indicating that the queuing device is empty, and the arbitration scheme takes into account the empty status information respectively received from the first and second queuing devices.
28 . The computer program product of claim 26 , wherein the information regarding retained transaction requests comprises ready status information indicating that the queuing device has a retained transaction, and the arbitration scheme takes into account the ready status information respectively received from the first and second queuing devices.
29 . The computer program product of claim 26 , wherein the information regarding retained transaction requests comprises empty status information indicating that the queuing device is empty, ready status information indicating that the queuing device has a retained transaction, and queue status information indicating the number of entries currently in the queuing device, wherein the arbitration scheme takes into account the empty status, ready status and queue status information respectively received from the first and second queuing devices.
30 . The computer program product of claim 26 , wherein the requested transactions are read and write operations and the arbitrator scheme determines which of the plurality of master devices are granted access to the target device to perform read or write operations.