Semiconductor device
View Patent ↗A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
1. A semiconductor device having a memory array including a plurality of nonvolatile memory cells formed in a semiconductor substrate, the memory array comprising:
a first nonvolatile memory cell having a first charge storage layer and a first gate electrode; and
a second nonvolatile memory cell having a second charge storage layer and a second gate electrode, wherein the second nonvolatile memory cell is arranged so that the first nonvolatile memory cell is adjoined in a first direction;
wherein the first and second electrodes extend in a second direction perpendicular to the first direction,
wherein the first electrode has a first contact section extending toward the second electrode in the first direction,
wherein the second electrode has a second contact section extending toward the first electrode in the first direction,
wherein the first and second contact positions are shifted in the second direction, respectively, and
wherein the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
2. A semiconductor device according to the claim 1 , further comprising:
a first insulating film formed over the memory array;
first and second plugs formed in the first insulating film; and
first and second wirings formed over the first insulating film;
wherein the first wiring is electrically connected to the first contact section via to the first plug, and
wherein the second wiring is electrically connected to the second contact section via to the second plug.
3. A semiconductor device according to the claim 2 ,
wherein the first and second wirings extend in the first direction.
4. A semiconductor device according to the claim 2 ,
wherein the diameter of the first plug is larger than the length of the first electrode in the first direction, and
wherein the diameter of the second plug is larger than the length of the second electrode in the first direction.
5. A semiconductor device according to the claim 1 ,
wherein an element isolation region is formed in the semiconductor substrate, and
wherein the first and second contact sections are arranged over the element isolation region.
6. A semiconductor device according to the claim 5 ,
wherein the element isolation region is formed of a second insulating film embedded into a trench formed in the semiconductor substrate.
7. A semiconductor device according to the claim 1 ,
wherein the first and second electrodes are formed in a sidewall form.
8. A semiconductor device according to the claim 1 ,
wherein silicide films are formed over the first electrode, the second electrode, the first contact section and the second contact section.
9. A semiconductor device according to the claim 8 , wherein the silicide films are cobalt silicide films.
10. A semiconductor device according to the claim 1 ,
wherein the first and second charge storage layers include a silicon nitride film, respectively.
11. A semiconductor device according to the claim 10 ,
wherein the first and second nonvolatile memory cells have third and fourth gate electrodes, respectively,
wherein the first and second electrodes are formed over sidewalls of the third and fourth gate electrodes, respectively, and
wherein the first and second charge storage layers are formed under the first and second electrodes, respectively.
12. A semiconductor device having a memory array including a plurality of nonvolatile memory cells, the memory array comprising:
a first nonvolatile memory cell having a first charge storage layer and a first gate electrode; and
a second nonvolatile memory cell having a second charge storage layer and a second gate electrode, wherein the second nonvolatile memory cell is arranged so that the first nonvolatile memory cell is adjoined in a first direction;
wherein the first and second electrodes extend in a second direction perpendicular to the first direction,
wherein the first electrode has a first contact section extending toward the second electrode in the first direction,
wherein the second electrode has a second contact section extending toward the first electrode in the first direction,
wherein the first and second contact positions are shifted in the second direction, respectively, and
wherein, at time of a write data operation of the first nonvolatile memory cell, the first and second electrodes are independently applied with different voltages, respectively.
13. A semiconductor device according to the claim 12 , further comprising:
a first insulating film formed over the memory array;
first and second plugs formed in the first insulating film; and
first and second wirings formed over the first insulating film,
wherein the first wiring is electrically connected to the first contact section via to the first plug, and
wherein the second wiring is electrically connected to the second contact section via to the second plug.
14. A semiconductor device according to the claim 13 ,
wherein the first and second wirings extend in the first direction.
15. A semiconductor device according to the claim 13 ,
wherein the diameter of the first plug is larger than the length of the first electrode in the first direction, and
wherein the diameter of the second plug is larger than the length of the second electrode in the first direction.
16. A semiconductor device according to the claim 12 ,
wherein an element isolation region is formed in the semiconductor substrate, and
wherein the first and second contact sections are arranged over the element isolation region.
17. A semiconductor device according to the claim 16 ,
wherein the element isolation region is formed of a second insulating film embedded into a trench formed in the semiconductor substrate.
18. A semiconductor device according to the claim 12 ,
wherein the first and second electrodes are formed in a sidewall form.
19. A semiconductor device according to the claim 12 ,
wherein silicide films are formed over the first electrode, the second electrode, the first contact section and the second contact section.
20. A semiconductor device according to the claim 19 , wherein the silicide films are cobalt silicide films.
21. A semiconductor device according to the claim 12 ,
wherein the first and second charge storage layers each include a silicon nitride film.
22. A semiconductor device according to the claim 21 ,
wherein the first and second nonvolatile memory cells have third and fourth gate electrodes, respectively,
wherein the first and second electrode are formed over sidewalls of the third and fourth gate electrodes, respectively, and
wherein the first and second charge storage layers are formed under the first and second electrodes, respectively.