System and method for detecting glitches on a high-speed interface
View Patent ↗The current invention provides a mechanism for detecting and recovering from glitches on data strobes. In one embodiment, data is captured from an interlace by a receiver using at least one data strobe that is provided by the transmitter along with the data. A write address counter that is clocked by the data strobe is used to count the active edges of the data strobe. A read address counter that is periodically synchronized with the write address counter, but that is clocked by an internal clock of the receiver, is used to count units of data being received from the interface. Periodically, the contents of the read and write counters are compared. If the contents are not the same, a glitch has occurred on the data strobe. The glitch is recoverable if it occurs on, or after, a last strobe edge of a data transfer.
1. A system having a receiver to receive data from an interface using a data strobe provided with the data, comprising:
write select logic to use predetermined edges of the data strobe to increment a counter and thereby generate addresses to a storage device of the receiver that will store the data;
read control logic coupled to receive from the write select logic one of the generated addresses, and to use the received address to generate addresses within the storage device from which the data is to be retrieved; and
compare logic coupled to the read control logic to compare a predetermined one of the addresses generated by the write select logic to a predetermined one of the addresses generated by the read control logic, and to thereby detect whether a glitch occurred on the data strobe.
2. The system of claim 1 , wherein data is provided in multiple transfers, and wherein the read control logic is periodically coupled to receive from the write select logic an address to be used to capture a portion of data for a next data transfer, whereby if a glitch occurred on an edge of the data strobe most recently received by the receiver, read control logic will be synchronized with the write select logic so that the data will not be corrupted.
3. The system of claim 1 , wherein the read control logic generates addresses using a clock signal of the receiver.
4. The system of claim 1 , and further including a buffer coupled to the storage device, the read control logic to utilize the addresses generated by the read control logic to transfer the data from the storage device to the buffer at intervals that are asynchronous to the data strobe.
5. The system of claim 4 , wherein the predetermined one of the addresses generated by the read control logic is a last address generated to read the data from the storage device.
6. The system of claim 1 , wherein the predetermined one of the addresses generated by the write select logic is an address generated using a last edge of the data strobe that was received with the data.
7. The system of claim 1 , further including parity detection logic to detect whether a parity error occurred on the data as it is read from the storage device.
8. The system of claim 1 , further including a maintenance processor coupled to receive from the compare logic an indication as to whether a glitch occurred on the data strobe, and to further receive an indication as to whether a parity error occurred on the data, and to thereby determine whether corruption of the data occurred.
9. The system of claim 1 , further including programmable logic to selectively disable one or more of a group consisting of
the compare logic from detecting a glitch on the data strobe; and
the read control logic from receiving from the write select logic the one of the generated addresses.
10. The system of claim 1 , wherein the data is provided in multiple transfers, each separated by an idle cycle, and wherein during each idle cycle, the compare logic is enabled to determine whether a glitch occurred on the data strobe.
11. A method of receiving data by a receiver from an interface using a data strobe provided with the data, comprising:
incrementing a counter in response to predetermined edges of the data strobe to generate one or more write addresses to a storage device that will store received data;
utilizing at least one of said generated write addresses to generate one or more read addresses for use in retrieving the data from the storage device; and
determining whether a predetermined one of the read addresses is the same as a predetermined one of the write addresses, and if not, providing an indication that a glitch occurred on the strobe.
12. The method of claim 11 further including repeating the steps of claim 11 for multiple data transfers, and wherein the predetermined one of the write addresses is a write address generated using a last-received active edge of the strobe of each of the data transfers.
13. The method of claim 11 , wherein data is received during multiple data transfers, and further including periodically synchronizing the read address to the write address in preparation for receipt of a next data transfer.
14. The method of claim 13 , wherein the synchronizing of the read address to the write address occurs at a time selected from a group consisting of:
following a reset; and
during an idle cycle of the interface that occurs between two successive ones of the multiple transfers.
15. The method of claim 11 further including providing two data strobes with the data, each to capture a predetermined portion of the data, and further including performing the steps of claim 11 for each of the two data strobes.
16. The method of claim 11 further including selectively disabling the providing of an indication that a glitch occurred on the strobe.
17. The method of claim 11 further including:
determining whether a parity error occurred on the data; and
determining, based on an indication of whether the parity error occurred and on an indication of whether the glitch was detected, whether data corruption occurred.