Testing of an integrated circuit with a plurality of clock domains
View Patent ↗An integrated circuit comprises a plurality of clock domains ( 10, 12 ). Test data is shifted into the integrated circuit through a scan chain ( 100, 14, 104 ). In a test mode a connection is interrupted between a functional output of a first clock domain ( 10 ) and a functional input of a second clock domain ( 12 ). Test data is applied from the scan chain ( 100, 14, 104 ) to the functional input and a test response is captured into from the functional output. A delay circuit ( 24, 28 ) is used to delay transfer of the test result from the scan cell ( 21 ) to the functional input when the test result is captured in the scan cell ( 21 ), to ensure that timing differences between the clock domains do not affect the test. Subsequently the test result is shifted through the scan chain.
1. A test prepared integrated circuit comprising
a first and second clock domain, comprising a first functional circuit with a functional output and second functional circuit with a functional input respectively;
a scan chain comprising a scan cell with a data input and a data output, the data input being coupled to the functional output of the first functional circuit; —a transparency multiplexer with a first and second multiplexed input and an output, the first and second multiplexer input being coupled to the functional output of the first functional circuit and the data output respectively, the output being coupled to the functional input of the second functional circuit; —a delay circuit coupled in series with the transparency multiplexer between the data output and the functional input.
2. A test prepared integrated circuit according to claim 1 , wherein the delay circuit is switchable between a first and second mode, wherein a first delay and a second delay or substantially no delay are realized respectively, dependent on whether the scan chain is in a test normal mode wherein test results are captured or a shift mode wherein test data is shifted respectively.
3. A test prepared integrated circuit according to claim 1 , wherein the delay circuit comprises a transparent/hold latch in series with the transparency multiplexer, and a control input coupled to a clock input of the scan cell, the latch being arranged to switch to a hold mode during a clock pulse for updating data in the scan cell.
4. A test prepared integrated circuit according to claim 3 , wherein the delay circuit is switchable between a first and second mode, wherein a first delay and a second delay or substantially no delay are realized respectively, dependent on whether the scan chain is in a test normal mode wherein test results are captured or a shift mode wherein test data is shifted respectively, the latch being arranged to switch to a hold mode during a clock pulse only for clock pulses that occur while the scan chain is in the test normal mode.
5. A test prepared integrated circuit according to claim 3 , comprising a test control circuit, having a first test clock output for supplying a first test clock signal to the first clock domain and a second test clock output for supplying a second test clock to the scan cell and the control input of the delay circuit, timed so that the scan cell is updated and the latch is set to hold before the first test clock causes an update in the first clock domain and the update is completed before the second clock signal switches the latch back to transparent.
6. A test prepared integrated circuit according to claim 1 , wherein the scan cell comprises
a scan multiplexer with a first and second multiplexed input and an output, the first and second multiplexed input being coupled to the data input and a preceding scan cell in the scan chain respectively;
a scan flip-flop with an input coupled to the multiplexed output of the scan multiplexer and an output coupled to the data output; via the series arrangement of the delay circuit and the transparency multiplexer; —wherein the first multiplexed input of the transparency multiplexer is coupled to the functional output of the first functional circuit via the output of the scan multiplexer and wherein a scan input of a next following scan cell after the scan cell in the scan chain is coupled to the output of the transparency multiplexer.
7. A test prepared integrated circuit according to claim 1 , wherein the delay circuit is coupled between the output of the scan cell and the second multiplexed input of the transparency multiplexer.
8. A method of testing an integrated circuit that comprises a plurality of clock domains using a scan chain, the method comprising
switching the integrated circuit to a test mode, wherein a connection is interrupted between a functional output of a first one of the clock domains and a functional input of a second one of the clock domains;
applying a part of test data from the scan chain to the functional input from a scan cell;
capturing a test response to the test data from the functional output into the scan cell;
using a delay circuit to delay transfer of the test result from the scan cell to the functional input when the test result is captured in the scan cell;
shifting the test result through the scan chain.
9. A method according to claim 8 , comprising at least one of the following:
using less delay of transfer from the scan cell during shifting than during capture, or no delay;
using an extended clock cycle, or a skipped clock pulse before resumption of shifting after capture.
10. A method according to claim 8 , comprising
keeping the delay circuit active during shifting;
using mutually different clocks for said first clock domain and the scan cell, timed so that the scan cell is updated and a latch at the output of the scan cell is set to hold before the clock of the first clock domain causes an update in the first clock domain and the update is completed before the second clock signal switches the latch back to transparent.