Voltage converter and display device comprising a voltage converter
View Patent ↗A booster circuit of a two-step booster structure is manufactured by NMOS single channel processes and has two basic booster circuits to raise a gate voltage of a charge transfer transistor. The gate voltage of the transistor is first raised at one basic booster circuit, and this raised voltage is further raised at the other basic booster circuit.
1. A voltage converter circuit for converting an input voltage and outputting a converted voltage, comprising
first to eighth transistors and first to fifth capacitor elements,
wherein:
a drain and a gate of said first transistor are connected to a first terminal, and a source of said first transistor is connected to a first node;
a drain of said second transistor is connected to said first terminal, a gate of said second transistor is connected to a second node, and a source of said second transistor is connected to said first node;
a drain of said third transistor is connected to said first terminal, a gate of said third transistor is connected to said first node, and a source of said third transistor is connected to said second node;
a drain of said fourth transistor is connected to said second node, a gate of said fourth transistor is connected to a third node, and a source of said fourth transistor is connected to a fourth node;
a drain of said fifth transistor is connected to said second node, a gate of said fifth transistor is connected to a second terminal, and a source of said fifth transistor is connected to said fourth node;
a drain of said sixth transistor is connected to said second node, a gate of said sixth transistor is connected to said fourth node, and a source of said sixth transistor is connected to said second terminal;
a drain and a gate of said seventh transistor are connected to said second node, and a source of said seventh transistor is connected to said third node;
a drain of said eighth transistor is connected to said second node, a gate of said eighth transistor is connected to said fourth node, and a source of said eighth transistor is connected to said third node;
said first capacitor element is connected between a first control signal input terminal and said first node;
said second capacitor element is connected between a second control signal input terminal and said fourth node;
said third capacitor element is connected between a third control signal input terminal and said third node;
said fourth capacitor element is connected between a fourth control signal input terminal and said second node;
said fifth capacitor element is connected at least either between said second terminal and ground or between said first terminal and ground; and
first to fourth control signals having different timings are input to said first to fourth control signal input terminals, respectively.
2. The voltage converter circuit according to claim 1 , wherein said first to fourth control signals have pulse waveforms, and when representing rise and fall timings of said first to fourth control signals by tA 1 , tA 2 , tB 1 , tB 2 , tC 1 , tC 2 , tP 1 and tP 2 , respectively, said timings are, in the earlier order, tP 1 , tC 1 , tB 1 , tP 2 =tC 2 =tB 2 , tA 1 and tA 2 .
3. A voltage converter circuit wherein two or more voltage converter circuits recited in claim 1 are connected in parallel, and phases of said first to fourth control signals are reversed between both said voltage converter circuits to supply current from said two or more voltage converter circuits to a common output terminal.
4. The voltage converter circuit according to claim 1 , wherein said first to eighth transistors are made of NMOS single channel transistors.
5. The voltage converter circuit according to claim 1 , wherein:
initial voltages are applied to said first and second capacitor elements via said first and fourth transistors, respectively, and voltages applied to the gates of said third and sixth transistors are raised in accordance with said first and second control signals, respectively to switch between said third and sixth transistors; and
an initial voltage is applied to said third capacitor element via said seventh transistor, a voltage applied to the gate of said fourth transistor is raised in accordance with said third control signal to raise a voltage applied to said fourth node.
6. A display device having the voltage converter circuit recited in claim 1 , comprising:
a display panel having a plurality of pixel electrodes disposed in a matrix shape;
a switching element for supplying a video signal to each of said pixel electrodes;
a video signal line for supplying said video signal to said switching element;
a scan signal line for supplying a scan signal which controls said switching element;
a first drive circuit for outputting said video signal, said first drive circuit being formed on said display panel by processes similar to processes of forming said switching element; and
a second drive circuit for outputting said scan signal,
wherein the voltage converter circuit recited in claim 1 is formed in said display panel by the processes similar to the processes of forming said switching element.
7. A display device having the voltage converter circuit recited in claim 1 wherein voltages generated by the voltage converter circuit recited in claim 1 are used for drive voltages of the display device.
8. A voltage converter circuit for converting an input voltage and outputting a converted voltage, comprising
first to eighth transistors and first to fifth capacitor elements,
wherein:
a drain and a gate of said first transistor are connected to a first terminal, and a source of said first transistor is connected to a first node;
a drain of said second transistor is connected to said first terminal, a gate of said second transistor is connected to a second node, and a source of said second transistor is connected to said first node;
a drain of said third transistor is connected to said first terminal, a gate of said third transistor is connected to said first node, and a source of said third transistor is connected to said second node;
said first capacitor is connected between a first control signal input terminal and said first node;
one or a plurality of circuit blocks are serially connected between the source of said third transistor and a second terminal, and in each said circuit block,
a drain of said fourth transistor is connected to said second node, a gate of said fourth transistor is connected to a third node, and a source of said fourth transistor is connected to a fourth node; a drain of said fifth transistor is connected to said second node, a gate of said fifth transistor is connected to said second terminal, and a source of said fifth transistor is connected to said fourth node; a drain of said sixth transistor is connected to said second node, a gate of said sixth transistor is connected to said fourth node, and a source of said sixth transistor is connected to said second terminal; a drain and a gate of said seventh transistor are connected to said second node, and a source of said seventh transistor is connected to said third node; a drain of said eighth transistor is connected to said second node, a gate of said eighth transistor is connected to said fourth node, and a source of said eighth transistor is connected to said third node; said second capacitor element is connected between a second control signal input terminal and said fourth node; said third capacitor element is connected between a third control signal input terminal and said third node; said fourth capacitor element is connected between a fourth control signal input terminal and said second node,
wherein said circuit block uses the gate of said seventh transistor as an input from a previous block and the source of said sixth transistor as an output to a next block;
said fifth capacitor element is connected at least either between said second terminal and ground or between said first terminal and ground; and
first to fourth control signals having different timings are input to said first to fourth control signal input terminals, respectively.
9. The voltage converter circuit according to claim 8 , wherein when representing said second to fourth control signals of said circuit block by CKB 1 , CKC 1 , CKP 1 , CKB 2 , CKC 2 , CKP 2 , . . . , CKBn, CKCn, CKPn and representing rise and fall timings of said second to fourth control signals by tBn 1 , tBn 2 , tCn 1 , tCn 2 , tpn 1 and tPn 2 , said timings are, in the earlier order, tPn 1 , tCn 1 , tBn 1 , tPn 2 =tCn 2 =tBn 2 .
10. The voltage converter circuit according to claim 8 , said second to fourth control signals of each of said circuit blocks have a phase shifted by a half period for each of said circuit blocks.
11. The voltage converter circuit according to claim 8 , wherein said first to eighth transistors are made of NMOS single channel transistors.
12. A display device having the voltage converter circuit recited in claim 8 , comprising:
a display panel having a plurality of pixel electrodes disposed in a matrix shape;
a switching element for supplying a video signal to each of said pixel electrodes;
a video signal line for supplying said video signal to said switching element;
a scan signal line for supplying a scan signal which controls said switching element;
a first drive circuit for outputting said video signal, said first drive circuit being formed on said display panel by processes similar to processes of forming said switching element;
a second drive circuit for outputting said scan signal,
wherein the voltage converter circuit recited in claim 8 is formed in said display panel by the processes similar to the processes of forming said switching element.
13. A display device having the voltage converter circuit recited in claim 8 wherein voltages generated by the voltage converter circuit recited in claim 8 are used for drive voltages of the display device.