Motor controller having a multifunction port
View Patent ↗In one aspect, a control circuit to control a speed of a motor includes a control logic circuit connected to a multifunction port. The control logic circuit is configured to receive a control signal provided at the multifunction port and to provide response signals based on the control signal to place the motor in at least two of a sleep mode, a brake mode and a pulse-width modulation (PWM) mode. The motor control circuit also includes an H-bridge circuit configured to control the motor based on the response signals.
1. A control circuit to control a speed of a motor, comprising:
a multifunction port configured to receive a control signal;
a control logic circuit connected to the multifunction port, the control logic circuit being configured to receive the control signal provided at the multifunction port and to provide response signals based on the control signal to place the motor in at least two of a sleep mode, a brake mode and a pulse-width modulation (PWM) mode; and
an H-bridge circuit configured to control the motor based on the response signals.
2. The control signal of claim 1 wherein the control logic circuit comprises a window comparator circuit.
3. The control signal of claim 1 wherein the response signals comprise an awake signal, a motor control signal and a brake signal.
4. The control circuit of claim 3 wherein the control logic circuit provides the brake signal enabling the brake mode when the control signal provided at the multifunction port is a negative high voltage level signal,
wherein the control logic circuit provides the awake signal to start the motor when the control signal is a high voltage level signal, and
wherein the control logic circuit provides the motor control signal to enable the PWM mode when the control signal is a PWM signal.
5. The control circuit of claim 3 wherein the motor control signal is proportional to the control signal provided at the multifunction port when the control signal provided at the multifunction port is a positive voltage.
6. The control circuit of claim 3 , further comprising a sleep logic circuit connected to the control logic circuit and configured to receive the motor control signal.
7. The control circuit of claim 6 wherein the sleep logic circuit provides the sleep signal enabling the sleep mode based on at least a rotor commutation signal.
8. The control circuit of claim 7 wherein the rotor commutation signal is generated from a magnetic field sensor sensing a magnetic field generated by the motor.
9. The control circuit of claim 6 wherein the sleep mode comprises a transistor in the H-bridge circuit being turned off.
10. The control circuit of claim 6 wherein the sleep logic circuit comprises at least one timer circuit configured to receive the motor control signal.
11. The control circuit of claim 6 wherein the sleep logic circuit comprises at least one speed determination circuit.
12. The control circuit of claim 6 wherein the sleep logic circuit provides the sleep signal to the control logic circuit.
13. The control circuit of claim 6 wherein the control logic circuit comprises a latch circuit, the latch circuit configured to be latched to one logic state based on the sleep signal.
14. A control circuit to control a speed of a motor, comprising:
a multifunction port configured to receive a control signal;
a control logic circuit connected to the multifunction port, the control logic circuit being configured to receive the control signal provided at the multifunction port and to provide response signals based on the control signal to place the motor in at least two of a sleep mode, a brake mode, a pulse-width modulation (PWM) and a reverse motor rotation mode; and
an H-bridge circuit configured to control the motor based on the response signals.
15. The control signal of claim 14 wherein the control logic circuit comprises a window comparator circuit.
16. The control signal of claim 14 wherein the response signals comprise an awake signal, a motor control signal, a sleep signal, a motor direction signal and a brake signal.
17. The control circuit of claim 16 wherein the control logic circuit provides the brake signal enabling the brake mode when the control signal is between two threshold voltages for a predetermined amount of time.
18. The control circuit of claim 17 wherein the control logic circuit comprises at least one timer circuit configured to receive the motor control signal and to provide the brake signal,
wherein the control logic circuit provides the motor control signal proportional to the control signal provided at the multifunction port when the control signal is between two threshold voltages for less than the predetermined amount of time.
19. The control circuit of claim 16 wherein the control logic circuit provides the awake signal to start the motor when the control signal provided at the multifunction port has a voltage higher than a positive threshold voltage, the motor starting in a first rotational direction when the motor direction signal is at a first logic state,
wherein the control logic circuit provides the awake signal to start the motor when the control signal provided at the multifunction port has a voltage lower than a negative threshold voltage, the motor starting in a second rotational direction when the motor direction signal is at a second logic state.
20. The control circuit of claim 16 wherein the control logic circuit provides the motor control signal to enable the PWM mode when the control signal is a PWM signal.
21. The control circuit of claim 16 wherein the control logic circuit comprises a speed determination circuit to provide the sleep signal when enabled by the brake signal and the motor velocity is below a threshold value.
22. The control circuit of claim 21 wherein the speed determination circuit provides the sleep signal enabling the sleep mode based on at least a rotor commutation signal.
23. The control circuit of claim 22 wherein the rotor commutation signal is generated from a magnetic field sensor sensing a magnetic field generated by the motor.
24. The control circuit of claim 21 wherein the sleep mode comprises a transistor in the H-bridge circuit being turned off.
25. The control circuit of claim 21 wherein the control logic circuit comprises a latch circuit, the latch circuit configured to be latched to one logic state based on the control signal provided at the multifunction port and reset by the sleep signal.