Semiconductor integrated circuit device having deposited layer for gate insulation
View Patent ↗A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.
1. A semiconductor integrated circuit device comprising:
a first MISFET including a first gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate and a first gate electrode formed over the first gate insulating film; and
a second MISFET including a second gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and a second gate electrode formed over the second gate insulating film,
a film thickness of the second gate insulating film being thinner than a film thickness of the first gate insulating film,
wherein the first gate insulating film includes a thermally oxidized film and a deposited film formed over the thermally oxidized film,
wherein the second gate insulating film includes a thermally oxidized film and a deposited film formed over the thermally oxidized film of the second gate insulating film,
wherein a film thickness of the deposited film of the second gate insulating film is thinner than a film thickness of the deposited film of the first gate insulating film, and
wherein the first element forming region, the second element forming region and a third element forming region are individually isolated by an element isolation region.
2. A semiconductor integrated circuit device according to claim 1 , wherein the deposited film of the first insulating film is formed by a vapor deposition method, and wherein the deposited film of the second insulating film is formed by a vapor deposition method.
3. A semiconductor integrated circuit device according to claim 2 , wherein a film thickness of the thermally oxidized film of the second gate insulating film is thinner than a film thickness of the thermally oxidized film of the first gate insulating film.
4. A semiconductor integrated circuit device according to claim 1 , wherein an operating voltage of the first MISFET is higher than an operating voltage of the second MISFET.
5. A semiconductor integrated circuit device comprising:
a first MISFET including a first gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate and a first gate electrode formed over the first gate insulating film;
a second MISFET including a second gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and a second gate electrode formed over the second gate insulating film,
a film thickness of the second gate insulating film being thinner than a film thickness of the first gate insulating film; and
a third MISFET including a third gate insulating film formed over a third element forming region of the main surface of the semiconductor substrate and a third gate electrode formed over the third gate insulating film,
a film thickness of the third gate insulating film being thinner than a film thickness of the second gate insulating film,
wherein the first gate insulating film includes a thermally oxidized film and a deposited film formed over the thermally oxidized film,
wherein the second gate insulating film includes a thermally oxidized film and a deposited film formed over the thermally oxidized film of the second gate insulating film,
wherein a film thickness of the deposited film of the second gate insulating film is thinner than a film thickness of the deposited film of the first gate insulating film,
wherein the third gate insulating film includes a thermally oxidized film, and
wherein the first element forming region, the second element forming region and the third element forming region are individually isolated by an element isolation region.
6. A semiconductor integrated circuit device according to claim 5 , wherein a film thickness of the thermally oxidized film of the third gate insulating film is thinner than a film thickness of the thermally oxidized film of the second gate insulating film.
7. A semiconductor integrated circuit device according to claim 6 , wherein a film thickness of the thermally oxidized film of the second gate insulating film is thinner than a film thickness of the thermally oxidized film of the first gate insulating film.
8. A semiconductor integrated circuit device according to claim 5 , wherein a film thickness of the thermally oxidized film of the third gate insulating film is thinner than a film thickness of the thermally oxidized film of the second gate insulating film, and wherein a film thickness of the thermally oxidized film of the second gate insulating film is thinner than a film thickness of the thermally oxidized film of the first gate insulating film.
9. A semiconductor integrated circuit device according to claim 5 , wherein the deposited film of the first gate insulating film is formed by a vapor deposition method, and wherein the deposited film of the second gate insulating film is formed by a vapor deposition method.
10. A semiconductor integrated circuit device according to claim 5 , wherein an operating voltage of the first MISFET is higher than an operating voltage of the third MISFET.
11. A semiconductor integrated circuit device according to claim 5 , wherein an operating voltage of the first MISFET is higher than an operating voltage of the second MISFET.
12. A semiconductor integrated circuit device according to claim 5 , wherein an operating voltage of the first MISFET is higher than an operating voltage of the second MISFET, and wherein an operating voltage of the second MISFET is higher than an operating voltage of the third MISFET.