E-fuse and method
View Patent ↗An e-fuse circuit, a method of programming the e-fuse circuit, and a design structure of the e-fuse circuit. The method includes in changing the threshold voltage of one selected field effect transistor of two field effect transistors connected to different storage nodes of the circuit so as to predispose the circuit place the storage nodes in predetermined and opposite states.
1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising:
a first field effect transistor having drain connected to a first storage node, a gate connected to a second storage node and a source connected to a first source/drain of a second field effect transistor, a second source/drain of said second field effect transistor connected to a first power supply line;
a third field effect transistor having a drain connected to said second storage node, a gate connected to said first storage node and a source connected to said first source/drain of said second transistor; and
means for sensing the states of said first and second storage nodes.
2. The design structure of claim 1 , wherein said first and third field effect transistors are p-channel field effect transistors.
3. The design structure of claim 2 , wherein said first power supply line is a high voltage line or Vdd line.
4. The design structure of claim 1 , wherein said first and third field effect transistors are n-channel field effect transistors.
5. The design structure of claim 4 , wherein said first power supply line is a low voltage or ground line.
6. The design structure of claim 1 , including:
a fourth field effect transistor having drain connected to said first storage node, a gate connected to said second storage node and a source connected to a second power supply line;
a fifth field effect transistor having a drain connected to said second storage node, a gate connected to said first storage node and a source connected to said second power supply line; and
wherein said first and third field effect transistors are of a first channel type and said fourth and fifth field effect transistor are of a second channel type different from said first type.
7. The design structure of claim 6 , further including:
a sixth field effect transistor having a first source/drain connected to first storage node, a second source/drain connected to said second storage node and a gate connected to a reset pin of said circuit;
a seventh field effect transistor having a drain connected to said first storage node, a source connected to said second terminal of said power supply and a gate connected to said reset pin; and
an eighth field effect transistor having a drain connected to said second storage node, a source connected to said second terminal of said power supply and a gate connected to said reset pin.
8. The design structure of claim 7 , wherein said fourth, fifth and sixth field effect transistors are of said second channel type.
9. The design structure of claim 7 , further including:
a ninth field effect transistor having a first source/drain connected to said first storage node, a gate connected to a first pass pin of said circuit and a second source/drain connected to a first data pin of a latch; and
a tenth field effect transistor having a first source/drain connected to said second storage node, a gate connected to said first pass pin of said circuit and a second source/drain connected to said second data pin of said latch.
10. The design structure of claim 9 , wherein said ninth and tenth field effect transistors are of said second channel type.
11. The design structure of claim 9 , further including:
an eleventh field effect transistor having a first source/drain connected to said first storage node, a gate connected to a second pass pin of said circuit and a second source/drain connected to said first data pin of said latch; and
a twelfth field effect transistor having a first source/drain connected to said second storage node, a gate connected to said second pass pin of said circuit and a second source connected to said second data pin of said latch.
12. The design structure of claim 11 , wherein said eleventh and twelfth field effect transistors are of said first channel type.
13. The design structure of claim 1 , including:
a latch having a first input/output coupled to said first storage node through a first bit switch and a second input/output coupled to said second storage node through a second bit switch, said first and second bit switches each comprising a p-channel field effect transistor and a n n-channel field effect transistor.
14. The design structure of claim 1 , wherein the design structure comprises a netlist.
15. The design structure of claim 1 , wherein the design structure resides on a GDS storage medium.
16. The design structure of claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.
17. The design structure of claim 1 , wherein a gate of said second field effect transistor is connected to a sense pin.