Semiconductor device
View Patent ↗The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
1. A semiconductor device comprising:
(a) a first chip mounting section having a first main surface and a second main surface disposed on the opposite side thereof;
(b) a first external terminal which is disposed around the first chip mounting section and supplies a first power supply potential;
(c) a second external terminal which is disposed around the first chip mounting section and supplies a second power supply potential lower than the first power supply potential;
(d) output external terminals formed integrally with the first chip mounting section;
(e) a first semiconductor chip mounted over a first main surface of the first chip mounting section and having a source-to-drain path connected in series between the first external terminal and the output external terminals;
(f) a second semiconductor chip mounted over the first main surface of the first chip mounting section and having a source-to-drain path connected in series between the output external terminals and the second external terminal;
(g) a first lead plate which electrically connects electrodes formed in a main surface of the first semiconductor chip and the first external terminal to each other;
(h) a second lead plate which electrically connects electrodes formed in a main surface of the second semiconductor chip and the second external terminal to each other;
(i) an encapsulator which seals the first semiconductor chip and the second semiconductor chip, and
(j) a radiating fin attached to a part of each of the first and second lead plates through an insulative adhesive, wherein the part of each of the first and second lead plates is exposed from the encapsulator,
wherein a p channel first field effect transistor is formed in the first semiconductor chip,
wherein an n channel second field effect transistor is formed in the second semiconductor chip,
wherein the first field effect transistor comprises:
a semiconductor substrate having a first surface and a second surface;
a trench formed from the first surface of the semiconductor substrate to the second surface thereof;
a gate insulating film formed over an inner wall surface of the trench;
a gate electrode formed over the gate insulating film;
p type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode; and
n type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions,
wherein the second field effect transistor comprises:
a semiconductor substrate having a first surface and a second surface;
a trench formed from the first surface of the semiconductor substrate to the second surface thereof;
a gate insulating film formed over an inner wall surface of the trench;
a gate electrode formed over the gate insulating film;
n type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode;
p type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions; and
a drain semiconductor region formed in the second surface, and
wherein the first semiconductor chip is disposed closer to the first external terminal than a center of the first chip mounting section.
2. The semiconductor device according to claim 1 , wherein the radiating fin is comprised of copper or aluminum.
3. The semiconductor device according to claim 1 , wherein the radiating fin includes a plurality of depressions and projections at an upper portion of the radiating fin.
4. A semiconductor device comprising:
(a) a first chip mounting section having a first main surface and a second main surface disposed on the opposite side thereof;
(b) a first external terminal which is disposed around the first chip mounting section and supplies a first power supply potential;
(c) a second external terminal which is disposed around the first chip mounting section and supplies a second power supply potential lower than the first power supply potential;
(d) output external terminals formed integrally with the first chip mounting section;
(e) a first semiconductor chip mounted over a first main surface of the first chip mounting section and having a source-to-drain path connected in series between the first external terminal and the output external terminals;
(f) a second semiconductor chip mounted over the first main surface of the first chip mounting section and having a source-to-drain path connected in series between the output external terminals and the second external terminal;
(g) a first lead plate which electrically connects electrodes formed in a main surface of the first semiconductor chip and the first external terminal to each other;
(h) a second lead plate which electrically connects electrodes formed in a main surface of the second semiconductor chip and the second external terminal to each other;
(i) an encapsulator which seals the first semiconductor chip and the second semiconductor chip, and
(j) a radiating fin attached to a part of each of the first and second lead plates through an insulative adhesive, wherein the part of each of the first and second lead plates is exposed from the encapsulator,
wherein an n channel first field effect transistor is formed in the first semiconductor chip,
wherein an n channel second field effect transistor is formed in the second semiconductor chip,
wherein the first field effect transistor comprises:
a semiconductor substrate having a first surface and a second surface;
a gate insulating film formed over the first surface of the semiconductor substrate;
a gate electrode formed over the gate insulating film;
n type semiconductor regions for a source and a drain, which are formed in the first surface and formed at both ends of the gate electrode; and
p type semiconductor regions for channel formation formed at a bottom face of the gate electrode and formed between the source and drain semiconductor regions,
wherein the second field effect transistor comprises:
a semiconductor substrate having a first surface and a second surface;
a trench formed from the first surface of the semiconductor substrate to the second surface thereof;
a gate insulating film formed over an inner wall surface of the trench;
a gate electrode formed over the gate insulating film;
n type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode;
p type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions; and
a drain semiconductor region formed in the second surface, and
wherein the first semiconductor chip is disposed closer to the first external terminal than a center of the first chip mounting section.
5. The semiconductor device according to claim 4 , wherein the radiating fin is comprised of copper or aluminum.
6. The semiconductor device according to claim 4 , wherein the radiating fin includes a plurality of depressions and projections at an upper portion of the radiating fin.