System and method for improved LBIST power and run time
View Patent ↗A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets. A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.
1. A method for improved Logic Built-In Self Test (LBIST), comprising:
providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules;
wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets; and
interleaving LBIST channel scan operations for each of the LBIST satellite modules, by the LBIST controller, though the plurality of control signal sets;
wherein each LBIST satellite module includes:
a pseudo random pattern generator (PRPG),
a plurality of scan latches coupled to the PRPG, the plurality of scan latches arranged into at least two LBIST channels, and
a multiple input shift register (MISR) coupled to the plurality of scan latches; and
wherein interleaving comprises:
for a first period, enabling scan operations for a first group of LBIST satellite modules and disabling scan operations for a second group of LBIST satellite modules, and
for a second period, disabling scan operations for the first group of LBIST satellite modules and enabling scan operations for the second group of LBIST satellite modules.
2. The method of claim 1 , wherein each control signal set comprises a clock enable (clock-en) signal and a scan enable (scan-en) signal.
3. The method of claim 1 , further comprising interleaving LBIST sequence phase operations for each of the LBIST satellite modules, by the LBIST controller, through the plurality of control signal sets.
4. The method of claim 1 , further comprising performing contemporaneous non-scan latch (NSL) fill operations for a partition of the LBIST domain.
5. The method of claim 1 , further comprising forming the plurality of LBIST satellite modules by dividing the LBIST domain into the plurality of LBIST satellite modules, wherein the LBIST domain comprises logic circuitry on a single integrated circuit (IC) chip.
6. The method of claim 1 , further comprising grouping the plurality of LBIST satellite modules into a plurality of partitions.
7. The method of claim 6 , wherein grouping comprises power analysis.
8. The method of claim 6 , wherein the plurality of partitions comprises two partitions.
9. The method of claim 6 , wherein the plurality of partitions comprises four partitions.
10. The method of claim 1 , wherein each LBIST satellite module comprises thirty-two LBIST channels.
11. The method of claim 10 , wherein each LBIST channel comprises less than 2,000 latches.
12. A system, comprising:
a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules, wherein each LBIST satellite module includes:
a pseudo random pattern generator (PRPG),
a plurality of scan latches coupled to the PRPG, the plurality of scan latches arranged into at least two LBIST channels, and
a multiple input shift register (MISR) coupled to the plurality of scan latches;
an LBIST controller coupled to the LBIST domain, the LBIST controller configured to provide a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets; and
the LBIST controller further configured to interleave LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets;
wherein interleaving comprises:
for a first period, enabling scan operations for a first group of LBIST satellite modules and disabling scan operations for a second group of LBIST satellite modules, and
for a second period, disabling scan operations for the first group of LBIST satellite modules and enabling scan operations for the second group of LBIST satellite modules.
13. The system of claim 12 , wherein each control signal set comprises a clock enable (clock-en) signal and a scan enable (scan-en) signal.
14. The system of claim 12 , wherein the LBIST controller is further configured to interleave LBIST sequence phase operations for each of the LBIST satellite modules, through the plurality of control signal sets.
15. The system of claim 12 , further comprising performing contemporaneous non-scan latch (NSL) fill operations for a partition of the LBIST domain.
16. The system of claim 12 , wherein the LBIST domain further comprises a plurality of partitions, each partition comprising a subset of the plurality of LBIST satellite modules.
17. The system of claim 12 , wherein each LBIST satellite module comprises thirty-two LBIST channels, and wherein each LBIST channel comprises less than 2,000 latches.
18. A computer program product comprising a computer useable medium including a computer readable program, wherein the computer readable program when executed on a computer causes the computer to:
provide a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules;
wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets; and
interleave LBIST channel scan operations for each of the LBIST satellite modules, by the LBIST controller, though the plurality of control signal sets;
wherein each LBIST satellite module includes:
a pseudo random pattern generator (PRPG),
a plurality of scan latches coupled to the PRPG, the plurality of scan latches arranged into at least two LBIST channels, and
a multiple input shift register (MISR) coupled to the plurality of scan latches; and
wherein interleaving comprises:
for a first period, enabling scan operations for a first group of LBIST satellite modules and disabling scan operations for a second group of LBIST satellite modules, and
for a second period, disabling scan operations for the first group of LBIST satellite modules and enabling scan operations for the second group of LBIST satellite modules.
19. The computer program product of claim 18 , wherein the computer readable program when executed on a computer further causes the computer to interleave LBIST sequence phase operations for each of the LBIST satellite modules, by the LBIST controller, though the plurality of control signal sets.
20. The computer program product of claim 18 , wherein the computer readable program when executed on a computer further causes the computer to perform contemporaneous non-scan latch (NSL) fill operations for a partition of the LBIST domain.