Non volatile memory
View Patent ↗An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.
1. A nonvolatile memory apparatus, comprising:
a nonvolatile memory array divided into plural blocks, each of which includes plural nonvolatile memory cells and has an area used for storing predetermined information; and
a control circuit,
wherein the predetermined information indicates that data writing to the block is not complete,
wherein the control circuit stores address information associated with a block having the predetermined information stored in the area thereof, and can output the address information in response to an instruction from outside.
2. A nonvolatile memory apparatus according to claim 1 ,
wherein the control circuit surveys the nonvolatile memory array to determine whether any block stores the predetermined information in the respective area thereof, after a power on reset operation.
3. A nonvolatile memory apparatus according to claim 2 ,
wherein the control circuit can output result information of the surveying to outside.
4. A nonvolatile memory apparatus according to claim 3 , further comprising a status register,
wherein the status register includes a status field for storing the result information, and
wherein the control circuit outputs the result information of the status register in response to receiving a status read command.