Integrated process for thin film resistors with silicides

1. A method of forming a semiconductor device, the method comprising:

forming at least one hard mask overlaying at least one layer of resistive material;

forming at least one opening to a working surface of a silicon substrate of the semiconductor device;

cleaning the semiconductor device with a diluted HF/HCL process, the HF/HCL process including,

applying a dilute of HF, and

applying a dilute of HCL;

after cleaning with the diluted HF/HCL process, forming a silicide contact junction in the at least one of the opening to the working surface of the silicon substrate;

forming interconnect metal layers; and

patterning the interconnect metal layers.

2. The method of claim 1 , wherein the dilute of HF and the dilute of HCL are not applied at the same time.

3. The method of claim 1 , further comprising:

forming at least one oxide layer between the working surface of the silicon substrate and the layer of resistive material.

4. The method of claim 1 , wherein the layer of resistive material is a SiCr layer.

5. The method of claim 1 , wherein the layer of resistive material is a NiCr layer.

6. The method of claim 1 , wherein the hard mask is at least one of a TiN layer and a TiW layer.

7. The method of claim 1 , wherein forming the silicide contact junction further comprises:

depositing Pt in the opening to form a PtSi layer.

8. The method of claim 1 , further comprising:

removing the hard mask with peroxide after the formation of the at least one silicide contact junction.

9. The method of claim 1 , further comprising:

patterning the resistive material layer to form a resistor.

10. The method of claim 1 , wherein patterning the interconnect metal layers, further comprises:

applying a dry etch to pattern a layer of AlCu of the interconnect metal layers; and

after the dry etch, applying a wet etch to pattern a layer of TiW of the interconnect metal layers.

11. The method of claim 9 , wherein patterning the resistive material layer, further comprises:

applying a SiCr wet etch.

12. A method of forming devices on a semiconductor wafer, the method comprising:

depositing an oxide layer overlaying the semiconductor wafer;

depositing a layer of SiCr;

depositing a mask layer of TiN overlaying the layer of SiCr;

patterning the layer of SiCr and TiN layer to a desired shape;

applying a dilute of HF,

after applying the dilute of HF, applying a dilute of HCL, wherein the HF and HCL form a HF/HCL cleaning process for the semiconductor wafer;

removing any remaining mask layer of TiN; and

depositing one or more interconnect metal layers.

13. The method of claim 12 , wherein applying a dilute of HF, further comprises:

applying a 40:1 dilute of HF for approximately 60 seconds.

14. The method of claim 12 , wherein applying a dilute of HCL further comprises:

applying a 6:1 dilute of HCL at approximately 50 C° for approximately 70 seconds.

15. The method of claim 12 , further comprising:

patterning a contact opening through the oxide layer to expose a portion of a working surface of the semiconductor wafer; and

depositing Pt to form a PtSi contact junction in the contact opening.

16. The method of claim 12 , further comprising:

patterning an opening through the one or more interconnect metal layers to the patterned layer of SiCr to form a thin film resistor.

17. The method of claim 12 , wherein patterning the layer of SiCr and TiN layer to a desired shape further comprises:

applying a TiN dry etch; and

applying a SiCr wet etch after the TiN dry etch.

18. The method of claim 12 , wherein patterning the layer of SiCr and TiN layer to a desired shape further comprises:

applying a TiN dry etch until the desired amount of TiN and SiCr layer is removed; and

applying at least one of a plasma and HF dip.

19. The method of claim 12 , further comprising:

forming at least one device junction in the semiconductor wafer,

forming at least one field oxide layer on the working surface of the semiconductor wafer; and

using the at least one field oxide layer as a mask in defining an edge of the at least one device junction.