MOSFET with isolation structure and fabrication method thereof
View Patent ↗A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.
1. An N-type metal oxide semiconductor field effect transistor (MOSFET), comprising:
a P-type substrate;
a first N-type buried layer and a P-type epitaxial layer, formed in the P-type substrate;
a first N-type diffusion region having N conductivity-type ions, forming a first N-well in the first N-type buried layer;
a first P-type diffusion region having P conductivity-type ions, forming a first P-type region in the first N-well;
a first drain diffusion region having N+ conductivity-type ions, forming a first drain region in the first N-type diffusion region;
a first source diffusion region having N+ conductivity-type ions, forming a first source region, wherein a first channel is formed between the first source region and the first drain region;
a first contact diffusion region having P+ conductivity-type ions, forming a first contact region, wherein the first P-type diffusion region surrounds the first source region and the first contact region;
a plurality of separated P-type diffusion regions having P conductivity-type ions, forming a plurality of separated P-type regions in the P-type epitaxial layer, so as to provide an isolation effect;
a first thin gate oxide layer and a first thick field oxide layer, formed on the P-type substrate;
a first gate, disposed on the first thin gate oxide layer and the first thick field oxide layer, for controlling an amount of current in the first channel;
a silicon oxide insulating layer, covering the first gate and the first thick field oxide layer;
a first drain metal contact, having a first metal electrode connected with the first drain diffusion region;
a first source metal contact, having a second metal electrode connected to the first source diffusion region and the first contact diffusion region; and
a first gap, formed between the first thick field oxide layer and the first P-type region, for raising a breakdown voltage of the N-type MOSFET.
2. The N-type MOSFET as claimed in claim 1 , wherein the first P-type region located in the first N-well is formed through a P-well manufacturing process.
3. The N-type MOSFET as claimed in claim 1 , wherein the first P-type region located in the first N-well is formed through a P-type body/base manufacturing process.
4. A P-type MOSFET, comprising:
a P-type substrate;
a second N-type buried layer and a P-type epitaxial layer, formed in the P-type substrate;
a second N-type diffusion region having N conductivity-type ions, forming a second N-well in the second N-type buried layer;
a second P-type diffusion region having P conductivity-type ions, forming a second P-type region in the second N-well;
a second drain diffusion region having P+ conductivity-type ions, forming a second drain region in the second P-type diffusion region;
a second source diffusion region having P+ conductivity-type ions, forming a second source region, wherein a second channel is formed between the second source region and the second drain region;
a second contact diffusion region having N+ conductivity-type ions, forming a second contact region, wherein the second N-type diffusion region surrounds the second source region and the second contact region;
a plurality of separated P-type diffusion regions having P conductivity-type ions, forming a plurality of separated P-type regions in the P-type epitaxial layer, so as to provide an isolation effect;
a second thin gate oxide layer and a second thick field oxide layer, formed on the P-type substrate;
a second gate, disposed on the second thin gate oxide layer and the second thick field oxide layer, for controlling an amount of current in the second channel;
a silicon oxide insulating layer, covering the second gate and the second thick field oxide layer;
a second drain metal contact, having a third metal electrode connected with the second drain diffusion region;
a second source metal contact, having a fourth metal electrode connected to the second contact diffusion region and the second source diffusion region; and
a second gap, formed between the second thick field oxide layer and the second N-well, for raising a breakdown voltage of the P-type MOSFET.
5. The P-type MOSFET as claimed in claim 4 , wherein the second P-type region located in the second N-well is formed through a P-well manufacturing process.
6. The P-type MOSFET as claimed in claim 4 , wherein the second P-type region located in the second N-well is formed through a P-type body/base manufacturing process.
7. A method of fabricating an N-type MOSFET, comprising:
forming a P-type substrate;
forming a first N-type buried layer and a P-type epitaxial layer in the P-type substrate;
forming a first N-well in the first N-type buried layer in a first N-type diffusion region having N conductivity-type ions;
forming a first P-type region in the first N-well in a first P-type diffusion region having P conductivity-type ions;
forming a first drain region in the first N-type diffusion region in a first drain diffusion region having N+ conductivity-type ions;
forming a first source region in a first source diffusion region having N+ conductivity-type ions, wherein a first channel is formed between the first source region and the first drain region;
forming a first contact region in a first contact diffusion region having P+ conductivity-type ions, wherein the first P-type diffusion region surrounds the first source region and the first contact region;
forming a plurality of separated P-type regions in the P-type epitaxial layer in a plurality of separated P-type diffusion regions having P conductivity-type ions, so as to provide an isolation effect;
forming a first thin gate oxide layer and a first thick field oxide layer on the P-type substrate;
disposing a first gate on the first thin gate oxide layer and the first thick field oxide layer, for controlling an amount of current in the first channel;
covering the first gate and the first thick field oxide layer with a silicon oxide insulating layer;
forming a first drain metal contact having a first metal electrode connected with the first drain diffusion region;
forming a first source metal contact having a second metal electrode connected to the first source diffusion region and the first contact diffusion region; and
forming a first gap between the first thick field oxide layer and the first P-type region, for raising a breakdown voltage of the N-type MOSFET.
8. The method of fabricating an N-type MOSFET as claimed in claim 7 , wherein the first P-type region located in the first N-well is formed through a P-well manufacturing process.
9. The method of fabricating an N-type MOSFET as claimed in claim 7 , wherein the first P-type region located in the first N-well is formed through a P-type body/base manufacturing process.
10. A method of fabricating a P-type MOSFET, comprising:
forming a P-type substrate;
forming a second N-type buried layer and a P-type epitaxial layer in the P-type substrate;
forming a second N-well in the second N-type buried layer in a second N-type diffusion region having N conductivity-type ions;
forming a second P-type region in the second N-well in a second P-type diffusion region having P conductivity-type ions;
forming a second drain region in the second P-type diffusion region in a second drain diffusion region having P+ conductivity-type ions;
forming a second source region in a second source diffusion region having P+conductivity-type ions, wherein a second channel is formed between the second source region and the second drain region;
forming a second contact region in a second contact diffusion region having N+ conductivity-type ions, wherein the second N-type diffusion region surrounds the second source region and the second contact region;
forming a plurality of separated P-type regions in the P-type epitaxial layer in a plurality of separated P-type diffusion regions having P conductivity-type ions, so as to provide an isolation effect;
forming a second thin gate oxide layer and a second thick field oxide layer on the P-type substrate;
disposing a second gate on the second thin gate oxide layer and the second thick field oxide layer, for controlling an amount of current in the second channel;
covering the second gate and the second thick field oxide layer with a silicon oxide insulating layer;
forming a second drain metal contact having a third metal electrode connected with the second drain diffusion region;
forming a second source metal contact having a fourth metal electrode connected to the second contact diffusion region and the second source diffusion region; and
forming a second gap between the second thick field oxide layer and the second N-well, for raising a breakdown voltage of the P-type MOSFET.
11. The method of fabricating a P-type MOSFET as claimed in claim 10 , wherein the second P-type region located in the second N-well is formed through a P-well manufacturing process.
12. The method of fabricating a P-type MOSFET as claimed in claim 10 , wherein the second P-type region located in the second N-well is formed through a P-type body/base manufacturing process.