Hybrid static and dynamic sensing for memory arrays
View Patent ↗A hybrid circuit for a memory includes: a skewed static logic gate circuit; a dynamic pre-discharge device coupled with the skewed static logic gate circuit for operating the static logic gate circuit as a dynamic circuit.
1. A semiconductor circuit for sensing logic states in a memory array, the circuit comprising:
a skewed static logic gate having an output and a plurality of inputs; and
a dynamic pre-conditioning device coupled with the output of the skewed static logic gate for operating the static logic gate as a dynamic circuit for sensing the logic state in a memory array cell.
2. The semiconductor circuit of claim 1 wherein the skewed static logic gate is a NAND gate.
3. The semiconductor circuit of claim 1 wherein the skewed static logic gate is a NOR gate.
4. The semiconductor circuit of claim 1 wherein the dynamic pre-conditioning device is an NMOS device.
5. The semiconductor circuit of claim 1 wherein the memory array is a static random access memory.
6. The semiconductor circuit of claim 1 wherein the skewed static logic gate is an inverter.
7. The semiconductor circuit of claim 4 wherein the NMOS device comprises:
a drain coupled to the output of the skewed static logic gate; and
a source coupled to a ground potential.
8. The semiconductor circuit of claim 1 wherein the memory array comprises a register file array.
9. A hybrid static and dynamic sensing structure for memory arrays, the sensing structure comprising:
a skewed static logic gate having an output and a plurality of inputs; and
a dynamic pre-discharge/restore device coupled with the output of the skewed static logic gate for operating the skewed static logic gate as a dynamic circuit for sensing a logic state in a memory array cell.
10. The sensing structure of claim 9 wherein the skewed static logic gate is a NAND gate.
11. The sensing structure of claim 9 wherein the skewed static logic gate comprises a high switch point for enabling fast sensing, wherein the switch point is set according to a desired noise robustness on a local bit line.
12. The sensing structure of claim 9 wherein the pre-discharge/restore device is an NMOS device.
13. The sensing structure of claim 9 wherein the memory array is a static random access memory.
14. The sensing structure of claim 9 wherein the skewed static logic gate is an inverter.
15. The sensing structure of claim 12 wherein the NMOS device has a drain coupled to the output of the skewed static logic gate and a source coupled to a ground potential.
16. The sensing structure of claim 9 wherein the memory array comprises a register file array.
17. The sensing structure of claim 9 wherein the sensing structure is configured for primary and secondary sensing.
18. An information processing system comprising:
a processor;
a memory coupled with the processor, the memory comprising a plurality of bit lines and a plurality of byte lines; said memory further comprising a sensing circuit comprising:
a skewed static logic gate having an output and a plurality of inputs; and
a dynamic pre-discharge device coupled with the output of the skewed static logic gate for operating the skewed static logic gate as a dynamic circuit for sensing a logic state in a memory array cell.
19. The information processing system of claim 18 wherein the skewed static logic gate is a NAND gate.
20. The information processing system of claim 18 wherein the skewed static logic gate is a NOR gate.