Quad SRAM based one time programmable memory

1. A one-time programmable memory cell, comprising:

a storage element having a first upper input, a second upper input opposite the first upper input, a first lower input, a second lower input opposite the first lower input, a first output, and a second output opposite the first output;

a first fuse coupled to the first upper input, wherein the first fuse, when programmed, acts as a pull-up device on the first output;

a second fuse coupled to the second upper input, wherein the second fuse, when programmed, acts as a pull-up device on the second output;

a third fuse coupled to the first lower input, wherein the third fuse, when programmed, acts a pull-down device on the first output; and

a fourth fuse coupled to the second lower input, wherein the fourth fuse, when programmed, acts a pull-down device on the second output.

2. The one-time programmable memory cell of claim 1 , wherein when the first fuse and fourth fuse are programmed, the storage element outputs a first value during a read operation, and when the second fuse and third fuse are programmed, the storage element outputs a second value during a read operation.

3. The one-time programmable memory cell of claim 1 wherein the storage element operates as an SRAM cell when the first fuse, the second fuse, the third fuse, and the fourth fuse are not programmed.

4. The one-time programmable memory cell of claim 1 , wherein the first fuse, the second fuse, the third fuse, and the fourth fuse are thin-oxide MOS transistors.

5. The one-time programmable memory cell of claim 4 , wherein at least one of the thin-oxide MOS transistors is an NMOS transistor.

6. The one-time programmable memory cell of claim 4 , wherein at least one of the thin-oxide MOS transistors is an NMOS transistor with a native V T implant.

7. The one-time programmable memory cell of claim 4 , wherein at least one of the thin-oxide MOS transistor is an NMOS transistor in N WELL .

8. The one-time programmable memory cell of claim 4 , wherein at least one of the thin-oxide MOS transistors is a PMOS transistor.

9. The one-time programmable memory cell of claim 1 , further comprising:

a first programming decoder coupled to the third fuse and the second fuse; and

a second programming decoder coupled to the fourth fuse and the first fuse.

10. The one-time programmable memory cell of claim 1 , wherein the storage element comprises:

a first inverter coupled to the first fuse and the third fuse; and

a second inverter coupled to the second fuse and the fourth fuse.

11. The one-time programmable memory cell of claim 1 further comprising:

a first buffer device coupled between the first fuse and the storage element;

a second buffer device coupled between the third fuse and the storage element;

a third buffer device coupled between the second fuse and the storage element; and

a fourth buffer device coupled between the fourth fuse and the storage element.

12. A non-volatile dual SRAM one-time programmable memory device, comprising:

a dual SRAM one-time programmable memory block including one or more dual SRAM one-time programmable memory cells, wherein a dual SRAM one-time programmable memory cell operates as an SRAM memory cell prior to programming and operates as a one-time programmable memory cell after programming;

an SRAM module coupled to the dual SRAM one-time programmable memory block, wherein the SRAM read/write module is configured to read from and write to one or more dual SRAM one-time programmable memory cells prior to programming; and

an one-time programmable module configured to program one or more one-time programmable memory cells and to read one or more one-time programmable memory cells after programming.

13. The memory device of claim 12 , wherein a one-time programmable memory cell comprises:

a storage element having a first upper input, a second upper input opposite the first upper input, a first lower input, a second lower input opposite the first lower input, a first output, and a second output opposite the first output;

a first fuse coupled to the first upper input, wherein the first fuse, when programmed, acts as a pull-up device on the first output;

a second fuse coupled to the second upper input, wherein the second fuse, when programmed, acts as a pull-up device on the second output;

a third fuse coupled to the first lower input, wherein the third fuse, when programmed, acts a pull-down device on the first output; and

a fourth fuse coupled to the second lower input, wherein the fourth fuse, when programmed, acts a pull-down device on the second output.

14. The memory device of claim 13 , wherein when the first fuse and fourth fuse are programmed, the storage element outputs a first value during a read operation, and when the second fuse and third fuse are programmed, the storage element outputs a second value during a read operation.

15. The memory device of claim 13 , wherein the first fuse, the second fuse, the third fuse, and the fourth fuse are thin-oxide MOS transistors.

16. The memory device of claim 15 , wherein at least one of the thin-oxide MOS transistors is an NMOS transistor.

17. The memory device of claim 15 , wherein at least one of the thin-oxide MOS transistors is an NMOS transistor with a native V T implant.

18. The memory device of claim 15 , wherein at least one of the thin-oxide MOS transistors is an NMOS transistor in N WELL .

19. The memory device of claim 15 , wherein at least one of the thin-oxide MOS transistors is a PMOS transistor.