Differential latch-based one time programmable memory

1. A one-time programmable memory cell, comprising:

a differential latching amplifier having a first input and a second input;

a first fuse device coupled to the first input of the differential latching amplifier; and

a second fuse device coupled to the second input of the differential latching amplifier,

wherein when the first fuse device is programmed, differential latching amplifier outputs a first value during a read operation, and when the second fuse device is programmed, differential latching amplifier outputs a second value during a read operation.

2. The one-time programmable memory cell of claim 1 , wherein the fuse device is a thin-oxide MOS transistor.

3. The one-time programmable memory cell of claim 2 , wherein the thin-oxide MOS transistor is an NMOS transistor.

4. The one-time programmable memory cell of claim 2 , wherein the thin-oxide MOS transistor is an NMOS transistor with a native V T implant.

5. The one-time programmable memory cell of claim 2 , wherein the thin-oxide MOS transistor is an NMOS transistor in N WELL .

6. The one-time programmable memory cell of claim 2 , wherein the thin-oxide MOS transistor is a PMOS transistor.

7. The one-time programmable memory cell of claim 1 , further comprising:

a third fuse device coupled to the first input of the differential latching amplifier; and

a fourth fuse device coupled to the second input of the differential latching amplifier.

8. The one-time programmable memory cell of claim 1 , further comprising:

a plurality of fuse devices coupled to the first input of the differential latching amplifier; and

a plurality of fuse devices coupled to the second input of the differential latching amplifier.

9. The one-time programmable memory cell of claim 7 , further comprising:

a first fuse select transistor coupled to a first fuse select line and to the first fuse;

a second fuse select transistor coupled to a second fuse select line and to the second fuse;

a third fuse select transistor coupled to a third fuse select line and to the third fuse; and

a fourth fuse select transistor coupled to a fourth fuse select line and to the fourth fuse.

10. The one-time programmable memory cell of claim of claim 1 , further comprising:

a first latch buffer transistor coupled at a gate to a first latch enable line, at a source to the first input of the differential latch amplifier, and at a drain to the first fuse; and

a second latch buffer transistor coupled at a gate to a second latch enable line, at a source to the second input of the differential latch amplifier, and at a drain to the second fuse.

11. The one-time programmable memory cell of claim 1 , further comprising:

a first fuse buffer transistor coupled at a gate to a first program decoder, at a source to ground, and at a drain to the first fuse; and

a second fuse buffer transistor coupled at a gate to a second program decoder, at a source to ground, and at a drain to the second fuse.

12. The one-time programmable memory cell of claim 1 , wherein when the first fuse is unprogrammed and the second fuse is unprogrammed, the differential latching outputs a random value.

13. The one-time programmable memory cell of claim 1 , wherein the differential latching amplifier includes a first output and a second output.

14. The one-time programmable memory cell of claim 13 , further comprising:

a first inverter coupled to the first output; and

a second inverter coupled to the second output.

15. A method for reading a one-time programmable memory cell having a differential latching amplifier coupled at a first input to a first fuse device and at a second input to a second fuse device, comprising:

providing a first read current to the first fuse device;

providing a second read current to the second fuse device,

outputting a first value when the first fuse device is programmed causing the voltage level at the first input of the differential amplifier is lower than a voltage level at the second input of the differential amplifier; and

outputting a second value when the second fuse device is programmed causing the voltage level at the first input of the differential amplifier is higher than the voltage level at the second input of the differential amplifier.

16. A one-time programmable memory device, comprising:

a plurality of one-time programmable memory cells arranged in a memory array, wherein a one-time programmable memory cell includes:

a differential latching amplifier having a first input and a second input,

a first fuse device coupled to the first input of the differential latching amplifier, and

a second fuse device coupled to the second input of the differential latching amplifier,

wherein when the first fuse device is programmed, differential latching amplifier outputs a first value during a read operation, and when the second fuse device is programmed, differential latching amplifier outputs a second value during a read operation.

17. The one-time programmable memory device of claim 16 , wherein the fuse device is a thin-oxide MOS transistor.

18. The one-time programmable memory device of claim 17 , wherein the thin-oxide MOS transistor is an NMOS transistor.

19. The one-time programmable memory device of claim 17 , wherein the thin-oxide MOS transistor is an NMOS transistor with a native V T implant.

20. The one-time programmable memory device of claim 17 , wherein the thin-oxide MOS transistor is an NMOS transistor in NWELL.

21. The one-time programmable memory device of claim 17 , wherein the thin-oxide MOS transistor is a PMOS transistor.