Methods of forming mixed gate CMOS with single poly deposition
View Patent ↗A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation. In this latter case the oxidized protective material is incorporated into the metal gate stack, which incorporation results in a novel CMOS structure.
1. A method for processing a CMOS structure, comprising:
in a first type FET device,
implementing a first gate insulator;
disposing over said first gate insulator a portion of a first gate stack, wherein said portion comprises at least one metal layer;
overlaying said first gate insulator and said portion with a protective material;
in a second type FET device,
implementing a second gate insulator by performing an oxidation,
wherein said protective material prevents damage to said first gate insulator and to said portion during said oxidation;
disposing polysilicon concomitantly over said first type FET device and over said second type FET device; and
patterning said polysilicon, wherein forming polysilicon layers for said first gate stack and for a second gate stack, wherein said second type FET device comprises said second gate stack.
2. The method of claim 1 , wherein said overlaying of said protective material comprises forming a top layer and sidewalls of said protective material.
3. The method of claim 1 , further comprising:
forming sidewalls out of a covering material for said first gate insulator and for said portion of said first gate stack.
4. The method of claim 1 , wherein said protective material is being selected in such manner as to have an oxide which is selectively removable with respect to said second gate insulator, wherein said selectively removable oxide is removed after said oxidation.
5. The method of claim 4 , wherein said protective material is selected to be Si 1-x Ge x , with x being 0.7<x≦1.
6. The method of claim 1 , wherein said protective material is being selected in such manner as to have an oxide which is electrically conductive, wherein said electrically conductive oxide is left in place after said oxidation, whereby said electrically conductive oxide is included in said first gate stack.
7. The method of claim 1 , wherein said first gate insulator is characterized as being a high-k gate insulator.
8. The method of claim 1 , wherein said first type FET device is characterized as being a metal gate device, and said second type FET device is characterized as being a polysilicon gate device.