Fabrication method of semiconductor integrated circuit device
View Patent ↗A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.
1. A fabrication method of semiconductor integrated circuit devices, comprising the steps of:
mounting a plurality of semiconductor integrated circuit devices, obtained by encapsulating a plurality of semiconductor chips, including a logic circuit device or CPU and a memory circuit device, in one package, in a plurality of test boards; and
conducting a memory test on each memory circuit device in the semiconductor integrated circuit devices while the test boards are placed in a thermostatic bath.
2. A fabrication method of semiconductor integrated circuit devices, comprising the steps of:
(a) taking one test board for which testing has been completed out of a thermostatic bath while testing is underway on a plurality of semiconductor integrated circuit devices mounted in a plurality of test boards, placed therein;
(b) dislodging the semiconductor integrated circuit devices from said one test board taken out;
(c) mounting a plurality of other semiconductor integrated circuit devices to be tested in said one test board from which the semiconductor integrated circuit devices have been dislodged therefrom; and
(d) placing said one test board mounted with said other semiconductor integrated circuit devices into the thermostatic bath and subjecting said one test board to the testing,
wherein in the thermostatic bath, first slots and second slots are different from each other in temperature.
3. A fabrication method of semiconductor integrated circuit devices, comprising the steps of:
(a) taking one test board for which testing has been completed out of a thermostatic bath by a handler while testing is underway on a plurality of semiconductor integrated circuit devices mounted in a plurality of test boards, placed therein;
(b) dislodging the semiconductor integrated circuit devices from said one test board taken out by the handler;
(c) sorting out and putting in the dislodged semiconductor integrated circuit devices into cooling, based on the test result, by the handler;
(d) mounting a plurality of other semiconductor integrated circuit devices to be tested in said one test board from which the semiconductor integrated circuit devices have been dislodged therefrom by the handler; and
(e) placing said one test board mounted with said other semiconductor integrated circuit devices into the thermostatic bath by the handler and subjecting said one test board to the testing,
wherein in the thermostatic bath, first slots and second slots are different from each other in temperature.