Semiconductor integrated circuit which generates internal clock signal for fetching input data synchronously with the internal clock signal without decrease of timing margin
View Patent ↗A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
1. A semiconductor integrated circuit comprising:
a clock input terminal inputted with a clock signal which repeats a cycle having a first level, a second level, and two edges;
a data input terminal inputted with a data signal;
a first internal clock generating circuit for generating a first internal clock signal which changes a signal in a mid-period between a (n+i−j)th edge of said clock signal and a (n+i+j+1)th edge of said clock signal (where i denotes an integer of 1 or larger, j denotes an integer of 0 or larger and n denotes an integer of i+j+2 or larger; and
a first latch circuit for latching said data signal input to said data input terminal according to said first internal clock signal,
wherein said (n+i−j)th edge is an edge of changing from said first level to said second level, and
wherein said (n+i+j1)th edge is an edge of changing from said second level to said first level.
2. The semiconductor integrated circuit according to claim 1 , further comprising:
a second internal clock generating circuit for generating a second internal clock signal which changes a signal in a mid-period between a (n+i−j+1)th edge of said clock signal and a (n+i+j2)th edge of said clock signal; and
a second latch circuit for latching said data signal input to said data input terminal according to said second internal clock signal,
wherein said (n+i−j+1)th edge is an edge of changing from said second level to said first level, and
wherein said (n+i+j2)th edge is an edge of changing from said first level to said second level.
3. The semiconductor integrated circuit according to claim 1 , further comprising:
a memory cell array in which a plurality of memory cells are arranged in an array,
wherein said memory cell can be written based on said data signal of said first and second latch circuits.
4. The semiconductor integrated circuit according to claim 2 , further comprising:
a plurality of static memory cells arranged in an array,
wherein said plurality of static memory cells can be written based on said data signal of said first and second latch circuit.
5. The semiconductor integrated circuit according to claim 4 ,
wherein said static memory cells are formed on a single semiconductor substrate.