IP Library Granted Patent US 7,593,269
Granted Patent B2
US 7,593,269 · App. 11/943,502 · Granted Sep 22, 2009

Differential flash memory programming technique

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Quick Facts
Patent No.
US 7,593,269
App. No.
11/943,502
Granted
Sep 22, 2009
Kind
B2
Abstract

The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in particular, saving a significant amount of time during the development and/or production phases of any equipment containing flash memory devices and also saving time during an updating or upgrading procedure of such an equipment already being in use. Accordingly, the invention proposes for programming a flash memory device to program only differences in information between data already stored in the flash memory device and new data to be stored.

Claims (21)

1. A flash memory programming apparatus, comprising:

means having a logic for comparing embedded data presently stored in a flash memory device and new or updated data to be stored or programmed in that flash memory device to identify differences in information between the embedded data and the respective new or updated data to be stored or programmed therein;

means for selectively erasing and/or programming only a sector having the differences in information in the embedded data with regard to the respective new or updated data;

means having a logic for programming an erased sector with the respective new or updated data;

means having a logic for supervising the placing of stored information or information to be stored in the flash memory device; and

means for storing information least likely to be changed at an address near the end of the respective flash memory address space of the flash memory device.

2. A flash memory programming apparatus according to claim 1 further comprising a linker means for controlling the ordering of data to be stored within sectors of the flash memory device.

3. A flash memory programming apparatus according to claim 1 further comprising means for performing a cyclic redundancy check for ensuring an accurate data comparison.

4. A flash memory programming apparatus according to claim 1 wherein the programming changes an amount of data in the erased sector.

5. A flash memory programming apparatus, comprising:

means having a logic for comparing embedded data presently stored in a flash memory device and new or updated data to be stored or programmed in that flash memory device to identify differences in information between the embedded data and the respective new or updated data to be stored or programmed therein;

means for selectively erasing and/or programming only a sector having the differences in information in the embedded data with regard to the respective new or updated data;

means having a logic for programming an erased sector with the respective new or updated data;

means having a logic for supervising the placing of stored information or information to be stored in the flash memory device; and

means for defining a new succeeding sector of the flash memory device and programming the new succeeding sector with the respective new or updated data.

6. A flash memory programming apparatus, comprising:

means having a logic for comparing embedded data presently stored in a flash memory device and new or updated data to be stored or programmed in that flash memory device to identify differences in information between the embedded data and the respective new or updated data to be stored or programmed therein;

means for selectively erasing and/or programming only a sector having the differences in information in the embedded data with regard to the respective new or updated data;

means having a logic for programming an erased sector with the respective new or updated data;

means having a logic for supervising the placing of stored information or information to be stored in the flash memory device; and

means for storing information least likely to be changed at an address near the beginning of the respective flash memory address space of the flash memory device.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2007
From: LOHSE, MARTIN A.; TUCHMAN, KENNETH A.
To: AGERE SYSTEMS INC.
Reel/Frame 020144/0720 →