Radio frequency amplifier with constant gain setting
View Patent ↗Radio frequency amplifier with constant gain setting. A circuitry that includes triple well connected MOSFETs is employed to eliminate body effects therein. The voltage gain as presented herein, being implemented using a ratio of certain elements within the circuitry, is immune to variations in temperature, power supply voltage, and process variations. One implementation employs an array of selectable MOSFETs to allow for more than one gain setting to be provided by the amplifier. Such an amplifier has a variable/selectable gain setting. An appropriately placed MOSFET is employed to provide the desired input impedance (e.g., 50Ω). This design can be implemented using multiple n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs) (some of which are triple well connected) and p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs), or alternatively using P-MOSFETs and N-MOSFETs.
1. An amplifier circuitry, the circuitry comprising:
first and second n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs), wherein:
a gate of the first N-MOSFET is directly connected to a gate of the second N-MOSFET; and
a gate width of the first N-MOSFET is less than a gate width of the second N-MOSFET; and
an input voltage is provided to the directly connected gates of the first N-MOSFET and the second N-MOSFET;
a third N-MOSFET, wherein:
a bias voltage is provided to a gate of the third N-MOSFET;
a source of the third N-MOSFET is coupled to a drain of the second N-MOSFET; and
an output voltage is provided from a drain of the third N-MOSFET; and
an inductor that is coupled between the drain of the third N-MOSFET and a power supply voltage.
2. The circuitry of claim 1 , wherein:
the circuitry is operable to amplify the input voltage by any one gain of a plurality of gains thereby generating the output voltage.
3. The circuitry of claim 1 , further comprising:
a fourth N-MOSFET forms a pair current mirror with the first N-MOSFET; and wherein:
a drain of the first N-MOSFET is coupled to a gate of the first N-MOSFET and also coupled to a gate of the fourth N-MOSFET.
4. The circuitry of claim 1 , further comprising:
a current supply; and wherein:
a drain of the first N-MOSFET is coupled to a gate of the first N-MOSFET; and
the current supply injects a current into a node of the coupled gate and drain of the first N-MOSFET.
5. The circuitry of claim 1 , further comprising:
a fourth N-MOSFET forms a pair current mirror with the first N-MOSFET, wherein:
the source of the fourth N-MOSFET is also coupled to a ground voltage; and
a drain of the first N-MOSFET is coupled to a gate of the first N-MOSFET and also coupled to a gate of the fourth N-MOSFET;
fifth and sixth N-MOSFETs, wherein:
each of the fifth N-MOSFET and the sixth N-MOSFET is implemented in a tri-well configuration such that a source of the fifth N-MOSFET is connected to a well of the fifth N-MOSFET and a source of the sixth N-MOSFET is connected to a well of the sixth N-MOSFET;
a gate of the fifth N-MOSFET is coupled to a gate of the sixth N-MOSFET;
a gate of the fifth N-MOSFET is coupled to a drain of the fifth N-MOSFET;
a source of the fifth N-MOSFET is coupled to the power supply voltage; and
a source of the sixth N-MOSFET is coupled to a drain of the third N-MOSFET.
6. The circuitry of claim 1 , further comprising:
a fourth N-MOSFET forms a pair current mirror with the first N-MOSFET, wherein:
the source of the fourth N-MOSFET is also coupled to a ground voltage; and
a drain of the first N-MOSFET is coupled to a gate of the first N-MOSFET and also coupled to a gate of the fourth N-MOSFET;
fifth and sixth N-MOSFETs, wherein:
each of the fifth N-MOSFET and the sixth N-MOSFET is implemented in a tri-well configuration such that a source of the fifth N-MOSFET is connected to a well of the fifth N-MOSFET and a source of the sixth N-MOSFET is connected to a well of the sixth N-MOSFET;
a gate of the fifth N-MOSFET is coupled to a gate of the sixth N-MOSFET;
a gate of the fifth N-MOSFET is coupled to a drain of the fifth N-MOSFET; and
a source of the sixth N-MOSFET is coupled to a drain of the third N-MOSFET;
first and second p-channel metal oxide semiconductor field-effect transistors (P-MOSFET), wherein:
a gate of the first P-MOSFET is coupled to the gate of the second N-MOSFET;
a drain of the first P-MOSFET is coupled to a gate of the first P-MOSFET and also coupled to the gate of the second P-MOSFET.
7. The circuitry of claim 6 , wherein:
a drain of the sixth N-MOSFET, a source of the first P-MOSFET, and a source of the second P-MOSFET are coupled to at least one additional power supply voltage.
8. The circuitry of claim 1 , wherein:
the circuitry is an integrated circuit.
9. The circuitry of claim 1 , wherein:
the circuitry is implemented within a wireless communication device.
10. An amplifier circuitry, the circuitry comprising:
first and second n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs), wherein:
a gate of the first N-MOSFET is coupled to a gate of the second N-MOSFET;
a gate width of the first N-MOSFET is less than a gate width of a second N-MOSFET; and
a drain of the first N-MOSFET is coupled to a gate of the first N-MOSFET; and
an input voltage is provided to the coupled gates of the first N-MOSFET and the second N-MOSFET;
a third N-MOSFET, wherein:
a bias voltage is provided to a gate of the third N-MOSFET;
a source of the third N-MOSFET is coupled to a drain of the second N-MOSFET; and
an output voltage is provided from a drain of the third N-MOSFET; and
an inductor that is coupled between the drain of the third N-MOSFET and a power supply voltage;
a fourth N-MOSFET forms a pair current mirror with the first N-MOSFET, wherein the coupled gate and drain of the first N-MOSFET is also coupled to a gate of the fourth N-MOSFET; and
a current supply that injects a current into a node of the coupled gate and drain of the first N-MOSFET; and wherein:
the circuitry is operable to amplify the input voltage by any one gain of a plurality of gains thereby generating the output voltage.
11. The circuitry of claim 10 , further comprising:
fifth and sixth N-MOSFETs, wherein:
each of the fifth N-MOSFET and the sixth N-MOSFET is implemented in a tri-well configuration such that a source of the fifth N-MOSFET is connected to a well of the fifth N-MOSFET and a source of the sixth N-MOSFET is connected to a well of the sixth N-MOSFET;
a gate of the fifth N-MOSFET is coupled to a gate of the sixth N-MOSFET;
a gate of the fifth N-MOSFET is coupled to a drain of the fifth N-MOSFET;
a source of the fifth N-MOSFET is coupled to the power supply voltage;
a source of the sixth N-MOSFET is coupled to a drain of the third N-MOSFET; and
a gate width of the sixth N-MOSFET is twice as large as a gate width of the fifth N-MOSFET.
12. The circuitry of claim 10 , further comprising:
fifth and sixth N-MOSFETs, wherein:
each of the fifth N-MOSFET and the sixth N-MOSFET is implemented in a tri-well configuration such that each of a source of the fifth N-MOSFET and a source of the sixth N-MOSFET is connected to a substrate of the circuitry;
a gate of the fifth N-MOSFET is coupled to a gate of the sixth N-MOSFET;
a gate of the fifth N-MOSFET is coupled to a drain of the fifth N-MOSFET; and
a source of the sixth N-MOSFET is coupled to a drain of the third N-MOSFET;
first and second p-channel metal oxide semiconductor field-effect transistors (P-MOSFET), wherein:
a gate of the first P-MOSFET is coupled to the gate of the second N-MOSFET;
a drain of the first P-MOSFET is coupled to a gate of the first P-MOSFET and also coupled to the gate of the second P-MOSFET.
13. The circuitry of claim 12 , wherein:
a drain of the sixth N-MOSFET, a source of the first P-MOSFET, and a source of the second P-MOSFET are coupled to at least one additional power supply voltage.
14. The circuitry of claim 10 , wherein:
the circuitry is an integrated circuit.
15. The circuitry of claim 10 , wherein:
the circuitry is implemented within a wireless communication device.
16. An amplifier circuitry, the circuitry comprising:
first and second n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs), wherein:
each of the first N-MOSFET and the second N-MOSFET is implemented in a tri-well configuration such that each of a source of the first N-MOSFET and a source of the second N-MOSFET is connected to a substrate of the circuitry;
a gate of the first N-MOSFET is coupled to a gate of the second N-MOSFET; and
a gate width of the first N-MOSFET is less than a gate width of a second N-MOSFET; and
an input voltage is provided to the coupled gates of the first N-MOSFET and the second N-MOSFET;
a third N-MOSFET, wherein:
a bias voltage is provided to a gate of the third N-MOSFET;
a source of the third N-MOSFET is coupled to a drain of the second N-MOSFET; and
an output voltage is provided from a drain of the third N-MOSFET; and
an inductor that is coupled between the drain of the third N-MOSFET and a first power supply voltage;
a fourth N-MOSFET forms a pair current mirror with the first N-MOSFET, wherein:
the source of the fourth N-MOSFET is also coupled to a ground voltage; and
a drain of the first N-MOSFET is coupled to a gate of the first N-MOSFET and also coupled to a gate of the fourth N-MOSFET;
fifth and sixth N-MOSFETs, wherein:
each of the fifth N-MOSFET and the sixth N-MOSFET is implemented in a tri-well configuration such that each of a source of the fifth N-MOSFET and a source of the sixth N-MOSFET is connected to a substrate of the circuitry;
a gate of the fifth N-MOSFET is coupled to a gate of the sixth N-MOSFET;
a gate of the fifth N-MOSFET is coupled to a drain of the fifth N-MOSFET; and
a source of the sixth N-MOSFET is coupled to a drain of the third N-MOSFET;
first and second p-channel metal oxide semiconductor field-effect transistors (P-MOSFET), wherein:
a gate of the first P-MOSFET is coupled to the gate of the second N-MOSFET;
a drain of the first P-MOSFET is coupled to a gate of the first P-MOSFET and also coupled to the gate of the second P-MOSFET; and
a drain of the sixth N-MOSFET, a source of the first P-MOSFET, and a source of the second P-MOSFET are coupled to a second power supply voltage; and wherein:
the sixth N-MOSFET is one N-MOSFET of a plurality of N-MOSFETs implemented such that a source of only the one N-MOSFET of the plurality of N-MOSFETs is coupled to the drain of the third N-MOSFET; and
the circuitry is operable to amplify the input voltage by any one gain of a plurality of gains thereby generating the output voltage.
17. The circuitry of claim 16 , further comprising:
a current supply; and wherein:
the current supply injects a current into a node of the coupled gate and drain of the first N-MOSFET.
18. The circuitry of claim 16 , wherein:
a gate width of the sixth N-MOSFET is twice as large as a gate width of the fifth N-MOSFET; and
a gate width of the first P-MOSFET is same as a gate width of the second P-MOSFET.
19. The circuitry of claim 16 , wherein:
the circuitry is an integrated circuit.
20. The circuitry of claim 16 , wherein:
the circuitry is implemented within a wireless communication device.