IP Library Granted Patent US 7,532,135
Granted Patent B1
US 7,532,135 · App. 11/945,065 · Granted May 12, 2009

Dual purpose serializer/de-serializer for point-to-point and point-to-multipoint communication

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Quick Facts
Patent No.
US 7,532,135
App. No.
11/945,065
Granted
May 12, 2009
Kind
B1
Abstract

A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.

Claims (22)

1. A serializer/de-serializer, comprising:

an operation mode management interface; and

a clock recovery module that is configurable to operate in a first mode capable of locking onto an incoming embedded clock within a first locking time period, and in a second mode capable of locking onto an incoming embedded clock within a second locking time period shorter than said first locking time period, wherein a configuration of said clock recovery module is based on data received at said operation mode management interface.

2. The serializer/de-serializer of claim 1 , further comprising configurable registers that store parameters for one of said first mode and said second mode.

3. The serializer/de-serializer of claim 1 , wherein said clock recovery module includes a phase locked loop.

4. The serializer/de-serializer of claim 1 , wherein said clock recovery module includes a delay locked loop.

5. The serializer/de-serializer of claim 1 , wherein said first locking time period is for use in a point-to-point communication network.

6. The serializer/de-serializer of claim 1 , wherein said second locking time period is for use in a point-to-multipoint communication network.

7. The serializer/de-serializer of claim 1 , wherein said first mode has a better jitter characteristic than said second mode.

8. A serializer/de-serializer, comprising:

a clock recovery module that is configurable to operate in a first mode capable of locking onto an incoming embedded clock within a first locking time period, and in a second mode capable of locking onto an incoming embedded clock within a second locking time period shorter than said first locking time period, wherein a configuration of said clock recovery module is based on data received at an operation mode management interface.

9. The serializer/de-serializer of claim 8 , further comprising configurable registers that store parameters for one of said first mode and said second mode.

10. The serializer/de-serializer of claim 8 , wherein said clock recovery module includes a phase locked loop.

11. The serializer/de-serializer of claim 8 , wherein said clock recovery module includes a delay locked loop.

12. The serializer/de-serializer of claim 8 , wherein said first locking time period is for use in a point-to-point communication network.

13. The serializer/de-serializer of claim 8 , wherein said second locking time period is for use in a point-to-multipoint communication network.

14. The serializer/de-serializer of claim 8 , wherein said first mode has a better jitter characteristic than said second mode.

15. A serializer/de-serializer method, comprising:

storing a parameter in a configurable register of a serializer/de-serializer, said parameter being received by said serializer/de-serializer via an operation mode management interface; and

configuring a clock recovery module of said serializer/de-serializer to operate in one of a first operating mode and a second operating mode, said configuring being based on said parameter stored in said configurable register, wherein said first operating mode is capable of locking onto an incoming embedded clock within a first locking time period, and said second operating mode is capable of locking onto an incoming embedded clock within a second locking time period shorter than said first locking time period.

16. The method of claim 15 , wherein said configuring comprises configuring a phase locked loop.

17. The method of claim 15 , wherein said configuring comprises configuring a delay locked loop.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2007
From: DIAB, WAEL WILLIAM
To: BROADCOM CORPORATION
Reel/Frame 020154/0011 →