Generic voltage tolerant low power startup circuit and applications thereof
View Patent ↗Circuits and systems including a startup circuit coupled to a reference source for providing startup current to the reference source wherein no transistor of the startup circuit experiences a stress condition and wherein the startup circuit consumes no static current following stabilized, steady-state operation of the reference source.
1. Apparatus comprising:
a power supply providing Vss and Vdd;
a reference voltage source coupled to Vss and Vdd for generating a reference voltage signal (NBIAS); and
a startup circuit coupled to Vss and Vdd and coupled to the reference voltage source to generate a startup signal applied to the reference voltage source to initiate operation of the reference voltage source,
wherein the startup circuit is configured to consume no static current once the reference voltage source reaches its normal operating state, and
wherein the startup circuit is configured to never generate a stress voltage in any of its transistors,
wherein the startup circuit comprises:
a fence capacitor (C 0 ) coupled to Vss and coupled to a node (CAP);
a first pmos transistor (M 0 ) having its gate coupled to a signal (PBIAS) generated by the reference voltage source and having its source coupled to Vdd and having its drain coupled to CAP, wherein PBIAS follows Vdd due to parasitic resistance within the reference voltage source;
a second pmos transistor (M 1 ) having its gate diode coupled to CAP and having its source coupled to Vdd and having its drain coupled to CAP;
a third pmos transistor (M 2 ) having its gate coupled to CAP and having its source coupled to Vdd and having its drain coupled to the reference voltage source to start current flow in the NBIAS signal path of the reference voltage source; and
wherein at least one of the first, second and third PMOS transistors has a maximum gate-source voltage (“stress voltage”) less than Vdd-Vss.
2. A startup circuit adapted for coupling to a reference voltage source, the startup circuit comprising:
a fence capacitor (C 0 ) coupled to a Vss voltage source and coupled to a node (CAP);
a first pmos transistor (M 0 ) having its gate coupled to a signal (PBIAS) generated by the reference voltage source and having its source coupled to a Vdd voltage source and having its drain coupled to CAP, wherein PBIAS follows Vdd due to parasitic resistance within the reference voltage source;
a second pmos transistor (M 1 ) having its gate diode coupled to CAP and having its source coupled to Vdd and having its drain coupled to CAP; and
a third pmos transistor (M 2 ) having its gate coupled to CAP and having its source coupled to Vdd and having its drain coupled to the reference voltage source to start current flow in the NBIAS signal path of the reference voltage source,
wherein the startup circuit is configured to apply a startup current to NBIAS in response to ramping up of Vdd,
wherein the startup circuit is configured to consume no static current once the reference voltage source reaches its normal operating state,
wherein the startup circuit is configured to never generate a stress voltage in M 1 , and
wherein at least one of the M 0 , M 1 and M 2 has a maximum gate-source voltage (“stress voltage”) less than Vdd-Vss.
3. The startup circuit of claim 2
wherein transistors M 0 , M 1 , and M 2 all have a maximum gate-source voltage (“stress voltage”) less than Vdd-Vss, and
wherein the startup circuit is configured to never generate a stress voltage in M 0 or M 1 or M 2 .