IP Library Granted Patent US 7,852,645
Granted Patent B2
US 7,852,645 · App. 11/954,498 · Granted Dec 14, 2010

Circuit and associated method for reducing power consumption in a power transformer

Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
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Quick Facts
Patent No.
US 7,852,645
App. No.
11/954,498
Granted
Dec 14, 2010
Kind
B2
Abstract

A method and circuit is provided for reducing power consumption in a power transformer, typically incorporated into an electrical or electronic device such as a consumer device. In an embodiment, a detection/isolation circuit is coupled to an input of a power transformer/rectifier via a switching device. The switching device can be, for example, a solid state relay. The detection/isolation circuit is configured to sense the occurrence of no-load conditions in the power transformer and responsively disengage the power transformer from a coupled source of power (e.g., wall outlet) via the coupled switching device.

Claims (32)

1. A circuit for reducing power consumption in a power transformer during low-load and no-load conditions, the circuit comprising:

a first solid state switching device coupled to an input of the power transformer, said first solid state switching device being configured to disengage said power transformer from a power source upon detecting said no-load and low-load conditions on said power transformer;

a second solid state switching device coupled to an output of said power transformer

a rectifier coupled to an output of said power transformer, said rectifier being configured to rectify an output voltage of said power transformer;

a super capacitor coupled in parallel to an output of said rectifier , said super capacitor being configured to store energy during a load condition and further being configured to provide energy during said low-load and no-load conditions;

a voltage sense module coupled to said super capacitor and configured to monitor continuously a voltage on said super capacitor and to output a first control signal upon detecting a low voltage condition on said super capacitor;

a current sense module coupled to an output of said power transformer, said current sense module being configured to detect a load on said power transformer and to output a second control signal upon detecting said load condition, and

a control circuit configured to receive said first control signal from said voltage sense module and to receive said second control signal from said current sense module and to output a close switch signal to said first and second solid state switching devices in response to receiving said first and second control signals;

wherein the voltage sense module and the current sense module receive power from the super capacitor.

2. A circuit according to claim 1 , further comprising a regulator module for regulating power distributed to said voltage sense module, said current sense module and said control circuit.

3. A circuit according to claim 2 , wherein the first and second solid state switching devices are solid state relays.

4. A circuit according to claim 1 , wherein said first and second solid state switching devices open and close substantially simultaneously.

5. A circuit according to claim 1 , wherein said detection of said low voltage condition comprises detecting a voltage on said super capacitor being substantially equal to a pre-determined threshold voltage.

6. A circuit according to claim 1 , wherein said capacitor is on the order of 1 farad.

7. A circuit according to claim 1 , wherein said power transformer is an element of a consumer device.

8. A circuit according to claim 1 , wherein said low-load condition is less than substantially 5 mW.

9. A circuit according to claim 1 , wherein said current sense module further comprises a sensing resistor for detecting a load on said power transformer.

10. A device having reduced power consumption during low-load and no-load conditions, comprising:

a rectifier configured to convert AC power to DC power;

a power transformer coupled to said rectifier;

a power reduction circuit configured to reduce power consumption during said low-load and no-load conditions, the power reduction circuit comprising:

(a) a first solid state switching device coupled to an input of the power transformer, said switching device configured to disengage said power transformer from a power source upon detecting said no-load and low-load conditions on said power transformer;

(b) second solid state switching device coupled to an output of said power transformer.

(c) a super capacitor coupled in parallel to an output of said power transformer, said a super capacitor being configured to store energy during a load condition and to provide energy during said low-load and no-load conditions;

(c) a voltage sense module coupled to said super capacitor and configured to monitor continuously a voltage on said super capacitor and to output a first control signal upon detecting a low voltage condition on said super capacitor;

(d) a current sense module coupled to an output of said power transformer, said current sense module being configured to detect a load on said power transformer and to output a second control signal upon detecting said load condition; and

(e) a control circuit configured to receive said first control signal from said voltage sense module, to receive said second control signal from said current sense module, and to output a close switch signal to said switching device in response to receiving said first and second control signals;

wherein the voltage sense module and the current sense module receive power from the super capacitor.

11. A device according to claim 10 , wherein the first and second solid state switching devices are solid state relays.

12. A device according to claim 10 , further comprising a regulator module for regulating power distributed to said voltage sense module, said current sense module and said control circuit.

13. A device according to claim 10 , wherein said detection of said low voltage condition comprises detecting a voltage on said super capacitor being substantially equal to a pre-determined threshold voltage.

14. A device according to claim 10 , wherein said device is a consumer device.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030369/0528 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2007
From: FOUQUET, JULIE ELIZABETH, MS.; LUM, RICHARD K. K.., MR.; BAUMGARTNER, RICHARD A., MR.
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
Reel/Frame 020232/0690 →
Continuity (1)
Related Publication 20090154206A1 · Jun 18, 2009