Granted Patent B2

US 7,672,188 · App. 11/954,791 · Granted Mar 2, 2010

Abstract

Claims (16)

1. A system for blocking multiple memory read port activation, comprising:

a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer; and

a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch;

wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch.

2. The system of claim 1 , wherein a logic-1 assertion of the first buffer output corresponds to a logic-0 assertion of the second input to the blocking switch, and the blocking switch is further configured to block the signal transmission between the input and the output of the blocking switch in response to the logic-0 assertion of the second input to the blocking switch thereby preventing a simultaneous logic-1 assertion of the first buffer output and the second buffer output.

3. The system of claim 1 , wherein a logic-0 assertion of the first buffer output corresponds to a logic-1 assertion of the second input to the blocking switch, and the blocking switch is further configured to pass the signal transmission between the input and the output of the blocking switch in response to the logic-1 assertion of the second input to the blocking switch thereby allowing a logic-1 or logic-0 assertion of the second buffer output dependent on an assertion of the second polarity hold latch output.

4. The system of claim 2 , wherein:

an input of the first polarity hold latch is connected to a first output of a memory read decoder;

an input of the second polarity hold latch is connected to a second output of the memory read decoder;

an output of the first buffer is connected to a first read port activation switch of a first read port of a memory cell;

an output of the second buffer is connected to a second read port activation switch of a second read port of the memory cell; and

in response to a simultaneous logic-1 assertion of the input of the first polarity hold latch and the second polarity hold latch via the first output and the second output of the memory read decoder respectively, the preventing of a simultaneous logic-1 assertion of the first buffer output and the second buffer output by the blocking switch thereby prevents the activation of the second read port by a logic-1 assertion of the second read port activation switch when the first read port is activated by a logic-1 assertion of the first report activation switch.

5. The system of claim 2 , wherein:

the second polarity hold latch comprises a first gated inverter having an output connected to an output of a second gated inverter, and an inverter having an input connected to the output of the first gated inverter and the output of the second gated inverter and an output connected to an input of the second gated inverter;

the blocking switch comprises a transmission gate having an output connected to a pull-up switch, wherein the transmission gate is deactivated and the pull-up switch is activated by the logic-0 assertion of the second input to the blocking switch, thereby setting the output of the blocking switch to a logic-1 assertion; and

the buffer comprises an inverter.

Assignments (8)