IP Library Granted Patent US 8,031,492
Granted Patent B2
US 8,031,492 · App. 11/960,695 · Granted Oct 4, 2011

PWM controller for compensating a maximum output power of a power converter

Assignee: System General Corp.
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Quick Facts
Patent No.
US 8,031,492
App. No.
11/960,695
Granted
Oct 4, 2011
Kind
B2
Abstract

A PWM controller having an oscillator, a control circuit and a two-level limiter is provided. The oscillator generates a pulse signal. The control circuit couples to the oscillator for generating a PWM signal in response to the pulse signal, wherein the PWM signal controls a power switch. The two-level limiter couples to the control circuit for generating a two-level limit signal in response to an on-time of the PWM signal, wherein the two-level limit signal is formed by a first-level signal and a second-level signal during a switching period of the PWM signal, and the first-level signal is used to limit the maximum output power of the power converter under a high-line input voltage with a heavy-load condition, and the second-level signal is used to limit the maximum output power of the power converter under a low-line input voltage with the heavy-load condition.

Claims (28)

1. A PWM controller for compensating a maximum output power of a power converter, comprising:

an oscillator, for generating a pulse signal;

a control circuit, coupled to the oscillator for generating a PWM signal in response to the pulse signal, wherein the PWM signal controls a power switch; and

a two-level limiter, coupled to the control circuit for generating a two-level limit signal in response to an on-time of the PWM signal, wherein the two-level limit signal is formed by a first-level signal and a second-level signal during a switching period of the PWM signal, and the first-level signal is used to limit the maximum output power of the power converter under a high-line input voltage with a heavy-load condition, and the second-level signal is used to limit the maximum output power of the power converter under a low-line input voltage with the heavy-load condition.

2. The PWM controller of claim 1 , wherein the two-level limiter comprises:

a comparing circuit, coupled to the control circuit for generating a switching signal in response to the PWM signal; and

a two-level compensation circuit, coupled to the comparing circuit for generating the two-level limit signal in response to the switching signal,

wherein the first-level signal is generated in response to the switching signal is logic-low, the second level signal is generated in response to the switching signal is logic-high.

3. The PWM controller of claim 2 , wherein the comparing circuit comprises:

a saw-tooth circuit, coupled to the control circuit for generating a saw-tooth signal in response to an on/off status of the PWM signal; and

a comparator, coupled to the saw-tooth circuit for comparing the saw-tooth signal with a reference signal to generate the switching signal.

4. A PWM controller for compensating a maximum output power of a power converter, comprising:

an oscillator, for generating a pulse signal;

a control circuit, coupled to the oscillator for generating a PWM signal in response to the pulse signal, wherein the PWM signal controls a power switch; and

a two-level limiter, coupled to the control circuit for generating a two-level limit signal in response to an on-time of the PWM signal, wherein the two-level limit signal is formed by a first-level signal and a second-level signal during a switching period of the PWM signal, and the first-level signal is used to limit the maximum output power of the power converter under a high-line input voltage with a heavy-load condition, and the second-level signal is used to limit the maximum output power of the power converter under a low-line input voltage with the heavy-load condition;

wherein the two-level limiter comprises:

a comparing circuit, coupled to the control circuit for generating a switching signal in response to the PWM signal; and

a two-level compensation circuit, coupled to the comparing circuit for generating the two-level limit signal in response to the switching signal; wherein the first-level signal is generated in response to the switching signal is logic-low, the second level signal is generated in response to the switching signal is logic-high;

wherein the comparing circuit comprises:

a saw-tooth circuit, coupled to the control circuit for generating a saw-tooth signal in response to an on/off status of the PWM signal; and

a comparator, coupled to the saw-tooth circuit for comparing the saw-tooth signal with a reference signal to generate the switching signal;

wherein the reference signal determines a holding period of the first-level signal, and the holding period is to solve an over-compensation problem under the high-line input voltage with the heavy-load condition.

5. A method for compensating a maximum output power of a power converter, comprising the steps of:

generating a pulse signal;

generating a PWM signal in accordance with the pulse signal, wherein the PWM signal controls a power switch; and

generating a two-level limit signal in accordance with an on-time of the PWM signal, wherein the two-level limit signal is formed by a first-level signal and a second-level signal during a switching period of the PWM signal.

6. The method of claim 5 , wherein the first-level signal is used to limit the maximum output power of the power converter under a high-line input voltage with a heavy-load condition.

7. The method of claim 5 , wherein the second-level signal is used to limit the maximum output power of the power converter under a low-line input voltage with a heavy-load condition.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046410/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042328/0318 →
CHANGE OF NAME Recorded May 2, 2016
From: SYSTEM GENERAL CORP.
To: FAIRCHILD (TAIWAN) CORPORATION
Reel/Frame 038594/0168 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2007
From: LIN, CHIEN YUAN; CHEN, TIN-WEI
To: SYSTEM GENERAL CORP.
Reel/Frame 020274/0456 →
Continuity (2)
Provisional Application 60944096 · Jun 14, 2007
Related Publication 20080310193A1 · Dec 18, 2008