Read only memory cell having multi-layer structure for storing charges and manufacturing method thereof
An exemplary read only memory cell ( 200 ) includes a semiconductor layer ( 220 ), a gate stack ( 230 ), and a gate electrode ( 240 ). The gate stack includes a tunnel film ( 231 ), a charge storing layer ( 232 ), and a block layer ( 233 ) sequentially stacked adjacent to the semiconductor layer. The gate electrode is adjacent to the block layer. The charge storing layer is configured to store charges when data is written to the read only memory cell. The charge storing layer comprises at least two sub-layers having different molecular structures of material such that a plurality of interfacial traps is provided where the at least two sub-layers adjoin each other. A method for manufacturing the read only memory cell is also provided.
1 . A read only memory cell, comprising:
a semiconductor layer;
a gate stack comprising a tunnel film, a charge storing layer, and a block layer sequentially stacked adjacent to the semiconductor layer; and
a gate electrode adjacent to the block layer;
wherein the charge storing layer is configured to store charge when data is written to the read only memory cell, and the charge storing layer comprises at least two sub-layers having different molecular structures of material such that a plurality of interfacial traps is provided where the at least two sub-layers adjoin each other.
2 . The read only memory cell as claimed in claim 1 , wherein the at least two sub-layers further have different modes in which two neighboring molecules combine.
3 . The read only memory cell as claimed in claim 1 , wherein the material of the charge storing layer comprises a selected one of silicon nitride (SiNx), aluminum oxide (AlOx), aluminum oxide (AlOx), silicon carbon nitride (SiCN), silicon nitride oxide (SiNO), silicon carbon (SiC), silicon carbon oxide (SiCO), silicon carbon oxide nitride (SiCON), and hafnium oxide nitride (HfON).
4 . The read only memory cell as claimed in claim 1 , wherein the at least two sub-layers are three sub-layers, which comprise a first sub-layer, a second sub-layer, and a third sub-layer sequentially stacked.
5 . The read only memory cell as claimed in claim 4 , wherein a thickness of the first sub-layer is in a range from 10 nanometers to 30 nanometers.
6 . The read only memory cell as claimed in claim 5 , wherein a thickness of the second sub-layer is in a range from 10 nanometers to 50 nanometers.
7 . The read only memory cell as claimed in claim 1 , wherein a thickness of the charge storing layer is in a range from 30 nanometers to 110 nanometers.
8 . The read only memory cell as claimed in claim 1 , wherein the read only memory cell has a configuration of a top-gate type insulated gate field effect transistor or a bottom-gate type insulated gate field effect transistor.
9 . A method for manufacturing a read only memory cell, the method comprising:
providing a substrate;
providing a semiconductor layer on the substrate;
forming a tunnel film on the semiconductor layer;
forming a charge storing layer on the tunnel film, which comprises at least two sub-layers having different molecular structures of material such that a plurality of interfacial traps is formed where the at least two sub-layers adjoin each other;
forming a block layer on the charge storing layer; and
forming a gate electrode on the block layer.
10 . The method for manufacturing a read only memory cell as claimed in claim 9 , wherein the at least two sub-layers are formed via providing at least two manufacturing conditions.
11 . The method for manufacturing a read only memory cell as claimed in claim 9 , wherein the charge storing layer comprises three sub-layers.
12 . The method for manufacturing a read only memory cell as claimed in claim 11 , wherein forming a charge storing layer on the tunnel film comprises: forming a first sub-layer on the tunnel film via a chemical vapor deposition method with a first deposition speed; forming a second sub-layer on the first sub-layer via the chemical vapor deposition method with a second deposition speed; and forming a third sub-layer on the second sub-layer via the chemical vapor deposition method with a third deposition speed.
13 . The method for manufacturing a read only memory cell as claimed in claim 12 , wherein the first, second, and third first deposition speeds are different from each other.
14 . The method for manufacturing a read only memory cell as claimed in claim 12 , wherein a thickness of the first sub-layer is in a range from 10 nanometers to 30 nanometers, and a thickness of the second sub-layer is in a range from 10 nanometers to 50 nanometers.
15 . The method for manufacturing a read only memory cell as claimed in claim 9 , wherein a thickness of the charge storing layer is in a range from 30 nanometers to 110 nanometers.
16 . The method for manufacturing a read only memory cell as claimed in claim 9 , wherein each of at least two sub-layers comprises a selected one of silicon nitride (SiNx), aluminum oxide (AlOx), aluminum oxide (AlOx), silicon carbon nitride (SiCN), silicon nitride oxide (SiNO), silicon carbon (SiC), silicon carbon oxide (SiCO), silicon carbon oxide nitride (SiCON), and hafnium oxide nitride (HfON).
17 . A method for manufacturing a read only memory cell, the method comprising:
providing a substrate;
forming a gate electrode on the substrate;
forming a block layer on the gate electrode;
forming a charge storing layer on the block layer, which comprises at least two sub-layers having different molecular structures of material such that a plurality of interfacial traps is formed where the at least two sub-layers adjoin each other;
forming a tunnel film on the charge storing layer; and
forming a semiconductor layer on the tunnel film.
18 . The method for manufacturing a read only memory cell as claimed in claim 17 , wherein the at least two sub-layers are formed via providing at least two manufacturing conditions.
19 . The method for manufacturing a read only memory cell as claimed in claim 17 , wherein each of the at least two sub-layers comprises a selected one of silicon nitride (SiNx), aluminum oxide (AlOx), aluminum oxide (AlOx), silicon carbon nitride (SiCN), silicon nitride oxide (SiNO), silicon carbon (SiC), silicon carbon oxide (SiCO), silicon carbon oxide nitride (SiCON), and hafnium oxide nitride (HfON).
20 . The method for manufacturing a read only memory cell as claimed in claim 17 , wherein forming a charge storing layer on the tunnel film comprises: forming a first sub-layer on the block layer via a chemical vapor deposition method with a first deposition speed; forming a second sub-layer on the first nitride layer via the chemical vapor deposition method with a second deposition speed; and forming a third sub-layer on the second nitride layer via the chemical vapor deposition method with a third deposition speed.