Memory sensing and latching circuit
View Patent ↗According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal.
1. A memory sensing and latching circuit comprising:
a sensing circuit for evaluating bit lines in a memory array and providing a sensed output;
a latching circuit comprising a dynamic one-shot circuit driven by said sensed output, a sense amplifier enable signal, and a precharge clock;
said latching circuit further comprising a storage circuit for storing a one-shot output of said dynamic one-shot circuit, said one-shot output being responsive to said sensed output.
2. The memory sensing and latching circuit of claim 1 , wherein said one-shot output is stored in said storage circuit during an evaluation of said sensed output.
3. The memory sensing and latching circuit of claim 2 , wherein said evaluation of said sensed output is performed responsive to said sense amplifier enable signal.
4. The memory sensing and latching circuit of claim 1 , wherein said sense amplifier enable signal and said precharge clock determine a precharge state of said one-shot output.
5. The memory sensing and latching circuit of claim 1 , wherein said sense amplifier enable signal determines a precharge state of said bit lines.
6. The memory sensing and latching circuit of claim 1 , wherein said dynamic one-shot circuit comprises first and second PFETs coupled between a supply voltage and said one-shot output, wherein said sense amplifier enable signal is coupled to a gate of said first PFET and said precharge clock is coupled to a gate of said second PFET.
7. The memory sensing and latching circuit of claim 1 , wherein said dynamic one-shot circuit comprises first and second NFETs coupled between said one-shot output and a ground, wherein said sensed output is coupled to a gate of said first NFET and said sense amplifier enable signal is coupled to a gate of said second NFET.
8. The memory sensing and latching circuit of claim 1 , wherein said sensing circuit comprises a drain-fed sense amplifier.
9. A method for evaluating and storing a sensed output of a sensing circuit, said sensing circuit coupled to bit lines in a memory array, said method comprising steps of:
inputting said sensed output, a sense amplifier enable signal, and a precharge clock into a dynamic one-shot circuit of a latching circuit;
evaluating and storing a one-shot output of said dynamic one-shot circuit in a storage circuit of said latching circuit, said one-shot output being responsive to said sensed output.
10. The method of claim 9 further comprising a step of precharging said bit lines.
11. The method of claim 9 further comprising a step of precharging said one-shot output prior to said step of evaluating and storing said one-shot output in said storage circuit.
12. The method of claim 9 , wherein said evaluating and storing is performed responsive to said sense amplifier enable signal.
13. The method of claim 10 , wherein said step of precharging said bit lines is performed responsive to said sense amplifier enable signal.
14. The method of claim 9 , wherein said sense amplifier enable signal and said precharge clock are inputted into respective gates of PFETs in said dynamic one-shot circuit, wherein said PFETs are coupled between a supply voltage and said one-shot output.
15. The method of claim 9 , wherein said sense amplifier enable signal and said sensed output are inputted into respective gates of NFETs in said dynamic one-shot circuit, wherein said NFETs are coupled between said one-shot output and a ground.
16. A latching circuit coupled to a sensing circuit, said sensing circuit for evaluating bit lines in a memory array and providing a sensed output, said latching circuit comprising:
a dynamic one-shot circuit driven by said sensed output, a sense amplifier enable signal, and a precharge clock;
a storage circuit for storing a one-shot output of said dynamic one-shot circuit, said one-shot output responsive to said sensed output;
said one-shot output being stored in said storage circuit during an evaluation of said sensed output.
17. The latching circuit of claim 16 , wherein said evaluation of said sensed output is responsive to said sense amplifier enable signal.
18. The latching circuit of claim 16 , wherein said sense amplifier enable signal and said precharge clock determine a precharge state of said one-shot output.
19. The latching circuit of claim 16 , wherein said dynamic one-shot circuit comprises first and second PFETs coupled between a supply voltage and said one-shot output, wherein said sense amplifier enable signal is coupled to a gate of said first PFET and said precharge clock is coupled to a gate of said second PFET.
20. The latching circuit of claim 16 , wherein said dynamic one-shot circuit comprises first and second NFETs coupled between said one-shot output and a ground, wherein said sensed output is coupled to a gate of said first NFET and said sense amplifier enable signal is coupled to a gate of said second NFET.