IP Library › Granted Patent US 8,244,791
Granted Patent B1
US 8,244,791 · App. 12/022,721 · Granted Aug 14, 2012

Fast carry lookahead circuits

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Quick Facts
Patent No.
US 8,244,791
App. No.
12/022,721
Granted
Aug 14, 2012
Kind
B1
Abstract

A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.

Claims (44)

1. A carry lookahead circuit for a fast carry adder comprising:

a carry-in signal node;

first, second, and third carry-input signal nodes;

first, second, and third propagate signal nodes;

first, second, and third local carry-out signal nodes;

a carry-out signal node;

a first buffer having an input and an output, the input coupled to the carry-in signal node and the output coupled to the first local-carry out signal node;

a first multiplexer having a first data input coupled to the first carry-input signal node, a second data input coupled to the output of the first buffer, a control input coupled to the first propagate signal node, and an output coupled to the second local carry-out signal node;

a second multiplexer having a first data input coupled to the second carry-input signal node, a second data input coupled to the first carry-input signal node, a control input coupled to the second propagate signal node, and an output;

a first AND gate having a first input coupled to the first propagate signal node, a second input coupled to the second propagate signal node, and an output;

a third multiplexer having a first data input coupled to the output of the second multiplexer, a second data input coupled to the carry-in signal node through the first buffer, a control input coupled to the output of the first AND gate, and an output coupled to the third local carry-out signal node;

a fourth multiplexer having a first data input coupled to the third carry-input signal node, a second data input coupled to the output of the second multiplexer, a control input coupled to the third propagate signal node, and an output;

a second AND gate having a first input coupled to the first propagate input node, a second input coupled to the second propagate input node, a third input coupled to the third propagate input node, and an output;

a fifth multiplexer having a first data input coupled to the output of the fourth multiplexer, a second data input coupled to the carry-in signal node, a control input coupled to the output of the AND gate, and an output coupled to the carry-out signal node.

2. The carry lookahead circuit of claim 1 , wherein:

the output of the first buffer is coupled to the first local carry-out signal node through a second buffer;

the output of the first multiplexer is coupled to the second local carry-out signal node through a third buffer;

the output of the third multiplexer is coupled to the third local carry-out signal node through a fourth buffer; and

wherein the first buffer is smaller than the second, third, and fourth buffers.

3. The carry lookahead circuit of claim 1 , wherein the output of the fifth multiplexer is coupled to the carry-out signal node through a buffer.

4. A carry lookahead circuit for a fast carry adder comprising:

a carry-in signal node;

first, second, third, and fourth carry-input signal nodes;

first, second, third, and fourth propagate signal nodes;

first, second, third, and fourth local carry-out signal nodes;

a carry-out signal node;

a first buffer having an input and an output, the input coupled to the carry-in signal node and the output coupled to the first local-carry out signal node;

a first multiplexer having a first data input coupled to the first carry-input signal node, a second data input coupled to the output of the first buffer, a control input coupled to the first propagate signal node, and an output coupled to the second local carry-out signal node;

a second multiplexer having a first data input coupled to the second carry-input signal node, a second data input coupled to the first carry-input signal node, a control input coupled to the second propagate signal node, and an output;

a first AND gate having a first input coupled to the first propagate signal node, a second input coupled to the second propagate signal node, and an output;

a third multiplexer having a first data input coupled to the output of the second multiplexer, a second data input coupled to the carry-in signal node through the first buffer, a control input coupled to the output of the first AND gate, and an output coupled to the third local carry-out signal node;

a fourth multiplexer having a first data input coupled to the third carry-input signal node, a second data input coupled to the output of the third multiplexer, a control input coupled to the third propagate signal node, and an output coupled to a fourth local carry-out signal node;

a fifth multiplexer having a first data input coupled to the fourth carry-input signal node, a second data input coupled to the third carry-input signal node, a control input coupled to the fourth propagate signal node, and an output;

a second AND gate having a first input coupled to the third propagate input node, a second input coupled to the fourth propagate input node, and an output;

a sixth multiplexer having a first data input coupled to the output of the fifth multiplexer, a second data input coupled to the output of the second multiplexer, a control input coupled to the output of the second AND gate, and an output;

a third AND gate having a first input coupled to the first propagate input node, a second input coupled to the second propagate input node, a third input coupled to the third propagate input node, a fourth input coupled to the fourth propagate input node and an output;

a seventh multiplexer having a first data input coupled to the output of the sixth multiplexer, a second data input coupled to the carry-in signal node, a control input coupled to the output of the AND gate, and an output coupled to the carry-out signal node.

5. The carry lookahead circuit of claim 4 , wherein:

the output of the first buffer is coupled to the first local carry-out signal node through a second buffer;

the output of the first multiplexer is coupled to the second local carry-out signal node through a third buffer;

the output of the third multiplexer is coupled to the third local carry-out signal node through a fourth buffer;

the output of the fourth multiplexer is coupled to the fourth local carry-out signal node through a fifth buffer; and

wherein the first buffer is smaller than the second, third, fourth, and fifth buffers.

6. The carry lookahead circuit of claim 4 , wherein the output of the seventh multiplexer is coupled to the carry-out signal node through a buffer.