Manufacturing method of semiconductor device
View Patent ↗A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi 2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
1. A manufacturing method of a semiconductor device having a MISFET, comprising the steps of:
(a) forming a gate insulating film of the MISFET over a semiconductor substrate;
(b) forming a gate electrode of the MISFET over the gate insulating film;
(c) forming semiconductor regions as source and drain regions of the MISFET in the semiconductor substrate;
(d) forming a refractory metal film over the semiconductor substrate including upper surfaces of the gate electrode and the semiconductor regions;
(e) performing a first heat treatment to cause a reaction between the refractory metal film and the gate electrode or the semiconductor regions to form refractory metal silicide layers;
(f) after the step (e), removing an unreacted portion of the refractory metal film by a first wet cleaning;
(g) after the step (f), performing a second heat treatment to cause a reaction between the refractory metal silicide layers and the gate electrode or the semiconductor regions;
(h) after the step (g), performing a second wet cleaning by using a solution containing hydrochloric acid and aqueous hydrogen peroxide;
(i) after the step (h), forming a first insulating film over the MISFET, wherein the first insulating film is formed by a plasma CVD method; and
(j) after the step (i), forming a second insulating film over the first insulating film, wherein the second insulating film is formed by a low-pressure CVD method, and wherein the thickness of the second insulating film is larger than the thickness of the first insulating film.
2. A manufacturing method of the semiconductor device according to claim 1 , further comprising steps:
(k) after the step (j), forming an interlayer insulating film over the second insulating film; and
(l) after the step (k), forming a contact hole connected to one of the semiconductor regions by etching the interlayer insulating film, the second insulating film and the first insulating film.
3. A manufacturing method of a semiconductor device according to claim 1 , wherein the MISFET constitutes an n channel MISFET.
4. A manufacturing method of a semiconductor device according to claim 1 , wherein the step (g) is performed at a higher temperature than the step (e).
5. A manufacturing method of a semiconductor device according to claim 1 , wherein the refractory metal film is a cobalt film.
6. A manufacturing method of a semiconductor device according to claim 1 , wherein the first and second insulating films are silicon nitride films.
7. A manufacturing method of a semiconductor device according to claim 1 , wherein the first insulating film is a silicon oxide film, and wherein the second insulating film is a silicon nitride film.
8. A manufacturing method of a semiconductor device according to claim 1 , wherein a channel formation region is provided, and is a region arranged under the gate electrode and arranged between the source and drain regions.
9. A manufacturing method of a semiconductor device according to claim 1 , wherein, in the step (j), the second insulating film is formed at a temperature of from 700 to 800° C.
10. A manufacturing method of the semiconductor device according to claim 1 , wherein, in the step (j), a silane-based gas is employed.
11. A manufacturing method of a semiconductor device having a MISFET, comprising the steps of:
(a) forming a gate insulating film of the MISFET over a semiconductor substrate;
(b) forming a gate electrode of the MISFET over the gate insulating film;
(c) forming semiconductor regions as source and drain regions of the MISFET in the semiconductor substrate;
(d) forming a refractory metal film over the semiconductor substrate including upper surfaces of the gate electrode and the semiconductor regions;
(e) performing a first heat treatment to cause a reaction between the refractory metal film and the gate electrode or the semiconductor regions to form refractory metal silicide layers;
(f) after the step (e), removing an unreacted portion of the refractory metal film by a first wet cleaning;
(g) after the step (f), performing a second heat treatment to cause a reaction between the refractory metal silicide layers and the gate electrode or the semiconductor regions;
(h) after the step (g), performing a second wet cleaning by using a solution containing hydrochloric acid and aqueous hydrogen peroxide;
(i) after the step (h), forming a first insulating film over the MISFET, wherein the first insulating film is generating a compression stress in a channel formation region of the MISFET; and
(j) after the step (i), forming a second insulating film over the first insulating film, wherein the second insulating film is generating a tensile stress in the channel formation region of the MISFET, and wherein the thickness of the second insulating film is larger than the thickness of the first insulating film.
12. A manufacturing method of the semiconductor device according to claim 11 , further comprising steps:
(k) after the step (k), forming an interlayer insulating film over the second insulating film; and
(l) after the step (k), forming a contact hole connected to one of the semiconductor regions by etching the interlayer insulating film, the second insulating film and the first insulating film.
13. A manufacturing method of a semiconductor device according to claim 11 , wherein the MISFET constitutes an n channel MISFET.
14. A manufacturing method of a semiconductor device according to claim 11 , wherein the step (g) is performed at a higher temperature than the step (e).
15. A manufacturing method of a semiconductor device according to claim 11 , wherein the refractory metal film is a cobalt film.
16. A manufacturing method of a semiconductor device according to claim 11 , wherein the first and second insulating films are silicon nitride films.
17. A manufacturing method of a semiconductor device according to claim 11 , wherein the first insulating film is a silicon oxide film, and wherein the second insulating film is a silicon nitride film.
18. A manufacturing method of a semiconductor device according to claim 11 , wherein the channel formation region is a region arranged under the gate electrode and arranged between the source and drain regions.
19. A manufacturing method of a semiconductor device according to claim 11 , wherein, in the step (j), the second insulating film is formed at a temperature of from 700 to 800° C.
20. A manufacturing method of the semiconductor device according to claim 11 , wherein, in the step (j), a silane-based gas is employed.
21. A manufacturing method of a semiconductor device having a MISFET, comprising the steps of:
(a) forming a gate insulating film of the MISFET over a semiconductor substrate;
(b) forming a gate electrode of the MISFET over the gate insulating film;
(c) forming semiconductor regions as source and drain regions of the MISFET in the semiconductor substrate;
(d) forming a refractory metal film over the semiconductor substrate including upper surfaces of the gate electrode and the semiconductor regions;
(e) performing a first heat treatment to cause a reaction between the refractory metal film and the gate electrode or the semiconductor regions to form refractory metal silicide layers;
(f) after the step (e), removing an unreacted portion of the refractory metal film by a first wet cleaning;
(g) after the step (f), performing a second heat treatment to cause a reaction between the refractory metal silicide layers and the gate electrode or the semiconductor regions;
(h) after the step (g), performing a second wet cleaning by using a solution containing hydrochloric acid and aqueous hydrogen peroxide;
(i) after the step (h), forming a first insulating film over the MISFET; and
(j) after the step (i), forming a second insulating film over the first insulating film, wherein the second insulating film is formed in the presence of more silane-based gas compared with the first insulating film, and wherein the thickness of the second insulating film is larger than the thickness of the first insulating film.
22. A manufacturing method of the semiconductor device according to claim 21 , further comprising steps:
(k) after the step (j), forming an interlayer insulating film over the second insulating film; and
(l) after the step (k), forming a contact hole connected to one of the semiconductor regions by etching the interlayer insulating film, the second insulating film and the first insulating film.
23. A manufacturing method of a semiconductor device according to claim 21 , wherein the MISFET constitutes an n channel MISFET.
24. A manufacturing method of a semiconductor device according to claim 21 , wherein the step (g) is performed at a higher temperature than the step (e).
25. A manufacturing method of a semiconductor device according to claim 21 , wherein the refractory metal film is a cobalt film.
26. A manufacturing method of a semiconductor device according to claim 21 , wherein the first and second insulating films are silicon nitride films.
27. A manufacturing method of a semiconductor device according to claim 21 , wherein the first insulating film is a silicon oxide film, and wherein the second insulating film is a silicon nitride film.
28. A manufacturing method of a semiconductor device according to claim 21 , wherein a channel formation region is provided, and is a region arranged under the gate electrode and arranged between the source and drain regions.
29. A manufacturing method of a semiconductor device according to claim 21 , wherein, in the step (j), the second insulating film is formed at a temperature of from 700 to 800° C.
30. A manufacturing method of a semiconductor device according to claim 21 , wherein the second insulating film is formed by using silane-based gas, and wherein the first insulating film is formed by not using silane-based gas.