Gigabit ethernet transceiver with analog front end
View Patent ↗Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
1. A programmable gain amplifier (PGA) comprising:
a plurality of impedances coupled in series to divide an input signal into a plurality of voltage levels;
a plurality of buffers, each coupled to receive one of the plurality of voltage levels; and
a plurality of switches, each operable to connect and disconnect one of the buffers from an operating current, thereby deactivating the associated amplifier.
2. The programmable gain amplifier as in claim 1 , wherein at least one of the plurality of switches is operable to disconnect its associated buffer by disconnecting the buffer from ground.
3. The programmable gain amplifier as in claim 1 , wherein at least one of the plurality of switches is operable to disconnect its associated buffer by disconnecting the buffer from a power supply voltage.
4. The programmable gain amplifier as in claim 1 , wherein the plurality of switches comprise semi-conductor devices.
5. The programmable gain amplifier as in claim 4 , wherein the semi-conductor devices comprise MOS (metal oxide semi-conductor) devices.
6. The programmable gain amplifier as in claim 1 , wherein the plurality of buffers comprise semi-conductor devices.
7. The programmable gain amplifier as in claim 6 , wherein the semi-conductor devices comprise MOS (metal oxide semi-conductor) devices.
8. The programmable gain amplifier as in claim 1 , wherein the plurality of buffers comprise buffer amplifiers.
9. A circuit for providing a programmable gain comprising:
a first programmable gain amplifier (PGA) comprising:
a first plurality of impedances coupled in series to divide an input signal into a first plurality of voltage levels;
a first plurality of buffers, each coupled to receive one of the first plurality of voltage levels; and
a first plurality of switches, each operable to connect and disconnect one of the first plurality of buffers from an operating current, thereby deactivating the associated buffer; and
a second PGA configured to receive a voltage level from one of the first plurality of buffers, the second PGA comprising:
a second plurality of impedances coupled in series to divide the received voltage level into a second plurality of voltage levels; and
a second plurality of switches, each operable to connect and disconnect one of the second plurality of voltages to a second buffer.
10. The circuit as in claim 9 , wherein at least one of the first plurality of switches is operable to disconnect its associated buffer by disconnecting the buffer from ground.
11. The circuit as in claim 9 , wherein at least one of the first plurality of switches is operable to disconnect its associated buffer by disconnecting the buffer from a power supply voltage.
12. The circuit as in claim 9 , wherein the first plurality of switches comprise semi-conductor devices.
13. The circuit as in claim 12 , wherein the semi-conductor devices comprise MOS (metal oxide semi-conductor) devices.
14. The circuit as in claim 9 , wherein the first plurality of buffers comprise semi-conductor devices.
15. The circuit as in claim 14 , wherein the semi-conductor devices comprise MOS (metal oxide semi-conductor) devices.
16. The circuit as in claim 9 , wherein the second plurality of switches comprise semi-conductor switches.
17. The circuit as in claim 16 , wherein the semi-conductor switches comprise MOS devices.
18. The circuit as in claim 9 , wherein the buffers comprise buffer amplifiers.